公开(公告)号：US11688784B2

公开(公告)日：2023-06-27

申请号：US17218307

申请日：2021-03-31

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Meng-Han Lin ,  Te-Hsin Chiu ,  Wei Cheng Wu

IPC: H01L29/00 ,  H01L29/423 ,  H01L29/10 ,  H01L29/78 ,  H01L29/08 ,  H01L29/66 ,  H01L21/762 ,  H01L29/06 ,  H01L21/28

CPC classification number: H01L29/42376 ,  H01L21/28123 ,  H01L21/76224 ,  H01L29/0692 ,  H01L29/0847 ,  H01L29/1033 ,  H01L29/4238 ,  H01L29/6659 ,  H01L29/66598 ,  H01L29/7833 ,  H01L29/7834 ,  H01L29/665

Abstract: The present disclosure, in some embodiments, relates to an integrated chip. The integrated chip includes an isolation structure arranged within a substrate. The isolation structure has one or more surfaces defining one or more trenches that are recessed below an uppermost surface of the isolation structure and that are disposed along opposing sides of an active region of the substrate. A conductive gate is arranged over the substrate between a source region and a drain region. The conductive gate extends into the one or more trenches disposed along opposing sides of the active region of the substrate. The conductive gate has an upper surface that continuously extends past opposing sides of the one or more trenches.

公开(公告)号：US11569251B2

公开(公告)日：2023-01-31

申请号：US16535431

申请日：2019-08-08

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Meng-Han Lin ,  Te-Hsin Chiu

IPC: H01L27/11526 ,  H01L29/49 ,  H01L27/02 ,  H01L29/423 ,  H01L29/08 ,  H01L21/28 ,  H01L21/3213 ,  H01L29/66 ,  H01L21/321 ,  H01L21/265

Abstract: An integrated circuit device includes a plurality of metal gates each having a metal electrode and a high-κ dielectric and a plurality of polysilicon gates each having a polysilicon electrode and conventional (non high-κ) dielectrics. The polysilicon gates may have adaptations for operation as high voltage gates including thick dielectric layers and area greater than one μm2. Polysilicon gates with these adaptations may be operative with gate voltages of 10V or higher and may be used in embedded memory devices.

公开(公告)号：US11488971B2

公开(公告)日：2022-11-01

申请号：US17104686

申请日：2020-11-25

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Meng-Han Lin ,  Te-Hsin Chiu ,  Wei Cheng Wu

IPC: H01L27/11536 ,  H01L21/027 ,  H01L21/28 ,  H01L21/3105 ,  H01L21/311 ,  H01L21/321 ,  H01L21/3213 ,  H01L21/762 ,  H01L21/768 ,  H01L27/11521 ,  H01L29/08 ,  H01L29/423 ,  H01L29/49 ,  H01L29/66 ,  H01L29/788 ,  H01L27/11524 ,  H01L27/11529 ,  H01L27/11531 ,  H01L27/1157 ,  H01L27/11573 ,  H01L21/8234

Abstract: Various embodiments of the present application are directed to an IC, and associated forming methods. In some embodiments, the IC comprises a memory region and a logic region integrated in a substrate. A memory cell structure is disposed on the memory region. A logic device is disposed on the logic region having a logic gate electrode separated from the substrate by a logic gate dielectric. A sidewall spacer is disposed along a sidewall surface of the logic gate electrode. A contact etch stop layer (CESL) is disposed along an upper surface of the substrate, extending upwardly along and in direct contact with sidewall surfaces of the pair of select gate electrodes within the memory region, and extending upwardly along the sidewall spacer within the logic region.

公开(公告)号：US20210082932A1

公开(公告)日：2021-03-18

申请号：US17104686

申请日：2020-11-25

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Meng-Han Lin ,  Te-Hsin Chiu ,  Wei Cheng Wu

IPC: H01L27/11536 ,  H01L29/788 ,  H01L29/423 ,  H01L29/49 ,  H01L29/08 ,  H01L29/66 ,  H01L21/3213 ,  H01L21/28 ,  H01L21/311 ,  H01L21/768 ,  H01L21/762 ,  H01L21/3105 ,  H01L21/321 ,  H01L21/027 ,  H01L27/11521

Abstract: Various embodiments of the present application are directed to an IC, and associated forming methods. In some embodiments, the IC comprises a memory region and a logic region integrated in a substrate. A memory cell structure is disposed on the memory region. A logic device is disposed on the logic region having a logic gate electrode separated from the substrate by a logic gate dielectric. A sidewall spacer is disposed along a sidewall surface of the logic gate electrode. A contact etch stop layer (CESL) is disposed along an upper surface of the substrate, extending upwardly along and in direct contact with sidewall surfaces of the pair of select gate electrodes within the memory region, and extending upwardly along the sidewall spacer within the logic region.

公开(公告)号：US20200013778A1

公开(公告)日：2020-01-09

申请号：US16574205

申请日：2019-09-18

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Meng-Han Lin ,  Te-Hsin Chiu ,  Wei Cheng Wu

IPC: H01L27/092 ,  H01L29/49 ,  H01L29/423 ,  H01L29/78 ,  H01L21/8238 ,  H01L29/66 ,  H01L21/28 ,  H01L21/762 ,  H01L29/40

Abstract: The present disclosure, in some embodiments, relates to an integrated chip. The integrated chip has a source region and a drain region. The drain region is separated from the source region by a channel region. An isolation structure surrounds the source region, the drain region, and the channel region. A gate structure is over the channel region. The gate structure includes a first gate electrode region having one or more first materials and a second gate electrode region having one or more second materials that are different than the one or more first materials. The second gate electrode region continuously extends between a first outermost sidewall directly over the isolation structure and a second outermost sidewall directly over the channel region.

公开(公告)号：US20190148507A1

公开(公告)日：2019-05-16

申请号：US15989606

申请日：2018-05-25

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Meng-Han Lin ,  Te-Hsin Chiu ,  Wei Cheng Wu

IPC: H01L29/423 ,  H01L29/10 ,  H01L21/762 ,  H01L29/08 ,  H01L29/66 ,  H01L29/78

Abstract: The present disclosure, in some embodiments, relates to a transistor device within an active area having a shape configured to reduce a susceptibility of the transistor device to performance degradation (e.g., the kink effect) caused by divots in an adjacent isolation structure. The transistor device has a substrate including interior surfaces defining a trench within an upper surface of the substrate. One or more dielectric materials are arranged within the trench. The one or more dielectric materials define an opening exposing the upper surface of the substrate. The opening has a source opening over a source region within the substrate, a drain opening over a drain region within the substrate, and a channel opening between the source opening and the drain opening. The source opening and the drain opening have widths smaller than the channel opening. A gate structure extends over the opening between the source and drain regions.

公开(公告)号：US11948974B2

公开(公告)日：2024-04-02

申请号：US17461476

申请日：2021-08-30

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Shih-Wei Peng ,  Te-Hsin Chiu ,  Jiann-Tyng Tzeng

IPC: H01L29/06 ,  H01L23/522 ,  H01L25/11 ,  H01L29/423 ,  H01L29/786

CPC classification number: H01L29/0673 ,  H01L23/5226 ,  H01L25/115 ,  H01L29/0649 ,  H01L29/42392 ,  H01L29/78618

Abstract: A semiconductor device including vertical transistors with a back side power structure, and methods of making the same are described. In one example, a described semiconductor structure includes: a gate structure including a gate pad and a gate contact on the gate pad; a first source region disposed below the gate pad; a first drain region disposed on the gate pad, wherein the first source region, the first drain region and the gate structure form a first transistor; a second source region disposed below the gate pad; a second drain region disposed on the gate pad, wherein the second source region, the second drain region and the gate structure form a second transistor; and at least one metal line that is below the first source region and the second source region, and is electrically connected to at least one power supply.

公开(公告)号：US20210217868A1

公开(公告)日：2021-07-15

申请号：US17218307

申请日：2021-03-31

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Meng-Han Lin ,  Te-Hsin Chiu ,  Wei Cheng Wu

IPC: H01L29/423 ,  H01L29/10 ,  H01L29/78 ,  H01L29/08 ,  H01L29/66 ,  H01L21/762 ,  H01L29/06 ,  H01L21/28

Abstract: The present disclosure, in some embodiments, relates to an integrated chip. The integrated chip includes an isolation structure arranged within a substrate. The isolation structure has one or more surfaces defining one or more trenches that are recessed below an uppermost surface of the isolation structure and that are disposed along opposing sides of an active region of the substrate. A conductive gate is arranged over the substrate between a source region and a drain region. The conductive gate extends into the one or more trenches disposed along opposing sides of the active region of the substrate. The conductive gate has an upper surface that continuously extends past opposing sides of the one or more trenches.

公开(公告)号：US11063044B2

公开(公告)日：2021-07-13

申请号：US16906031

申请日：2020-06-19

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Meng-Han Lin ,  Te-Hsin Chiu ,  Wei Cheng Wu

IPC: H01L21/00 ,  H01L27/092 ,  H01L29/49 ,  H01L29/423 ,  H01L29/78 ,  H01L21/8238 ,  H01L29/66 ,  H01L21/28 ,  H01L21/762 ,  H01L29/40 ,  H01L29/51

Abstract: The present disclosure relates to a method of forming an integrated chip. The method includes forming an isolation structure within a substrate. The isolation structure surrounds a device region of the substrate. A sacrificial gate material is formed over the isolation structure and the device region of the substrate. A part of the sacrificial gate material is removed and a second metal is deposited where the part of the sacrificial gate material was removed. A remainder of the sacrificial gate material is subsequently removed and a first metal is deposited where the remainder of the sacrificial gate material was removed. The first metal is different than the second metal.

公开(公告)号：US10998315B2

公开(公告)日：2021-05-04

申请号：US16887138

申请日：2020-05-29

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Meng-Han Lin ,  Te-Hsin Chiu ,  Wei Cheng Wu

IPC: H01L29/00 ,  H01L27/092 ,  H01L29/49 ,  H01L29/423 ,  H01L29/78 ,  H01L21/8238 ,  H01L29/66 ,  H01L21/28 ,  H01L21/762 ,  H01L29/40 ,  H01L29/51

Abstract: The present disclosure relates to an integrated chip. The integrated chip includes a source region and a drain region disposed within an upper surface of a substrate. One or more dielectric materials are disposed within a trench within the substrate. The trench surrounds the source region and the drain region. A gate structure is disposed over the substrate between the source region and the drain region. The gate structure includes a first gate metal having a first sidewall and a second gate metal having a first outer sidewall that contacts the first sidewall directly over the upper surface of the substrate.