公开(公告)号：US09875967B2

公开(公告)日：2018-01-23

申请号：US15464759

申请日：2017-03-21

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Tai-I Yang ,  Cheng-Chi Chuang ,  Yung-Chih Wang ,  Tien-Lu Lin

IPC: H01L23/528 ,  H01L23/532 ,  H01L21/768

CPC classification number: H01L23/5283 ,  H01L21/76802 ,  H01L21/76804 ,  H01L21/76807 ,  H01L21/7682 ,  H01L21/76831 ,  H01L21/76834 ,  H01L21/76843 ,  H01L21/76877 ,  H01L21/76879 ,  H01L23/5221 ,  H01L23/5226 ,  H01L23/53238 ,  H01L23/53295 ,  H01L2221/1063 ,  H01L2924/0002 ,  H01L2924/00

Abstract: The present disclosure relates to an interconnect structure. In some embodiments, the interconnect structure has a first conductive body arranged within a first dielectric layer over a substrate. A first air-gap separates sidewalls of the first conductive body from the first dielectric layer. A barrier layer is arranged on sidewalls of the first conductive body at a location between the first conductive body and the first air-gap. The first air-gap is defined by a sidewall of the barrier layer and an opposing sidewall of the first dielectric layer.

公开(公告)号：US20170194259A1

公开(公告)日：2017-07-06

申请号：US15464759

申请日：2017-03-21

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Tai-I Yang ,  Cheng-Chi Chuang ,  Yung-Chih Wang ,  Tien-Lu Lin

IPC: H01L23/528 ,  H01L23/532 ,  H01L21/768

CPC classification number: H01L23/5283 ,  H01L21/76802 ,  H01L21/76804 ,  H01L21/76807 ,  H01L21/7682 ,  H01L21/76831 ,  H01L21/76834 ,  H01L21/76843 ,  H01L21/76877 ,  H01L21/76879 ,  H01L23/5221 ,  H01L23/5226 ,  H01L23/53238 ,  H01L23/53295 ,  H01L2221/1063 ,  H01L2924/0002 ,  H01L2924/00

Abstract: The present disclosure relates to an interconnect structure. In some embodiments, the interconnect structure has a first conductive body arranged within a first dielectric layer over a substrate. A first air-gap separates sidewalls of the first conductive body from the first dielectric layer. A barrier layer is arranged on sidewalls of the first conductive body at a location between the first conductive body and the first air-gap. The first air-gap is defined by a sidewall of the barrier layer and an opposing sidewall of the first dielectric layer.

公开(公告)号：US09633897B2

公开(公告)日：2017-04-25

申请号：US15170059

申请日：2016-06-01

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Tai-I Yang ,  Cheng-Chi Chuang ,  Yung-Chih Wang ,  Tien-Lu Lin

IPC: H01L21/768 ,  H01L23/532 ,  H01L23/522

CPC classification number: H01L23/5283 ,  H01L21/76802 ,  H01L21/76804 ,  H01L21/76807 ,  H01L21/7682 ,  H01L21/76831 ,  H01L21/76834 ,  H01L21/76843 ,  H01L21/76877 ,  H01L21/76879 ,  H01L23/5221 ,  H01L23/5226 ,  H01L23/53238 ,  H01L23/53295 ,  H01L2221/1063 ,  H01L2924/0002 ,  H01L2924/00

Abstract: The present disclosure relates to a method of forming an interconnect structure. In some embodiments, the method is performed by forming a trench within a first dielectric layer and forming sacrificial spacers along sidewalls of the trench. The trench is filled with a conductive material, and the sacrificial spacers are removed after the trench has been filled with the conductive material. A second dielectric layer is formed over the first dielectric layer to leave an air-gap in a region from which the sacrificial spacers were removed.

公开(公告)号：US09583383B2

公开(公告)日：2017-02-28

申请号：US15224728

申请日：2016-08-01

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chia-Tien Wu ,  Tien-Lu Lin

IPC: H01L23/48 ,  H01L23/50 ,  H01L29/40 ,  H01L21/768 ,  H01L21/02 ,  H01L23/532 ,  H01L23/528

CPC classification number: H01L21/7682 ,  H01L21/02178 ,  H01L21/02258 ,  H01L21/76807 ,  H01L21/76822 ,  H01L21/76826 ,  H01L21/76829 ,  H01L21/76843 ,  H01L21/76849 ,  H01L21/76877 ,  H01L23/5222 ,  H01L23/528 ,  H01L23/53228 ,  H01L23/53238 ,  H01L23/53266 ,  H01L23/5329 ,  H01L23/53295 ,  H01L2221/1047 ,  H01L2924/0002 ,  H01L2924/00

Abstract: An aluminum (Al) layer is formed over a semiconductor substrate. A selective portion of the Al layer is removed to form openings. The Al layer is anodized to obtain an alumina dielectric layer with a plurality of pores. The openings are filled with a conductive interconnect material. The pores are widened to form air gaps and a top etch stop layer is formed over the alumina dielectric layer.

Abstract translation: 在半导体衬底上形成铝（Al）层。 去除Al层的选择性部分以形成开口。 将Al层进行阳极氧化，得到具有多个孔的氧化铝介电层。 开口填充有导电互连材料。 孔被加宽以形成气隙，并且在氧化铝介质层上形成顶部蚀刻停止层。

公开(公告)号：US09390965B2

公开(公告)日：2016-07-12

申请号：US14135785

申请日：2013-12-20

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Tai-I Yang ,  Cheng-Chi Chuang ,  Yung-Chih Wang ,  Tien-Lu Lin

IPC: H01L21/768 ,  H01L23/532 ,  H01L23/522

CPC classification number: H01L23/5283 ,  H01L21/76802 ,  H01L21/76804 ,  H01L21/76807 ,  H01L21/7682 ,  H01L21/76831 ,  H01L21/76834 ,  H01L21/76843 ,  H01L21/76877 ,  H01L21/76879 ,  H01L23/5221 ,  H01L23/5226 ,  H01L23/53238 ,  H01L23/53295 ,  H01L2221/1063 ,  H01L2924/0002 ,  H01L2924/00

Abstract: An interconnect structure includes a first low-k dielectric layer formed over a substrate. A first metal line is disposed in the first low-k dielectric layer. The first metal line includes a first conductive body with a first width and an up landing pad with a second width. The first width is smaller than the second width. The interconnect structure further includes a first air-gap adjacent to sidewalls of the first conductive body. The interconnect structure also includes a second low-k dielectric layer formed over the first low-k dielectric layer and a first via in the second low-k dielectric layer and disposed on the up landing pad.

Abstract translation: 互连结构包括在衬底上形成的第一低k电介质层。 第一金属线设置在第一低k电介质层中。 第一金属线包括具有第一宽度的第一导电体和具有第二宽度的向上着陆垫。 第一宽度小于第二宽度。 互连结构还包括与第一导电体的侧壁相邻的第一气隙。 互连结构还包括形成在第一低k电介质层上的第二低k电介质层和第二低k电介质层中的第一通孔，并设置在上焊垫上。

公开(公告)号：US20150279724A1

公开(公告)日：2015-10-01

申请号：US14739413

申请日：2015-06-15

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chia-Tien Wu ,  Tien-Lu Lin

IPC: H01L21/768

CPC classification number: H01L21/7682 ,  H01L21/02178 ,  H01L21/02258 ,  H01L21/76807 ,  H01L21/76822 ,  H01L21/76826 ,  H01L21/76829 ,  H01L21/76843 ,  H01L21/76849 ,  H01L21/76877 ,  H01L23/5222 ,  H01L23/528 ,  H01L23/53228 ,  H01L23/53238 ,  H01L23/53266 ,  H01L23/5329 ,  H01L23/53295 ,  H01L2221/1047 ,  H01L2924/0002 ,  H01L2924/00

Abstract: An aluminum (Al) layer is formed over a semiconductor substrate. A selective portion of the Al layer is removed to form openings. The Al layer is anodized to obtain an alumina dielectric layer with a plurality of pores. The openings are filled with a conductive interconnect material. The pores are widened to form air gaps and a top etch stop layer is formed over the alumina dielectric layer.

Abstract translation: 在半导体衬底上形成铝（Al）层。 去除Al层的选择性部分以形成开口。 将Al层进行阳极氧化，得到具有多个孔的氧化铝介电层。 开口填充有导电互连材料。 孔被加宽以形成气隙，并且在氧化铝介质层上形成顶部蚀刻停止层。

公开(公告)号：US09076790B1

公开(公告)日：2015-07-07

申请号：US14151158

申请日：2014-01-09

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chia-Tien Wu ,  Tien-Lu Lin

IPC: H01L23/48 ,  H01L23/50 ,  H01L29/40 ,  H01L23/522 ,  H01L23/532 ,  H01L21/768 ,  H01L21/02

CPC classification number: H01L21/7682 ,  H01L21/02178 ,  H01L21/02258 ,  H01L21/76807 ,  H01L21/76822 ,  H01L21/76826 ,  H01L21/76829 ,  H01L21/76843 ,  H01L21/76849 ,  H01L21/76877 ,  H01L23/5222 ,  H01L23/528 ,  H01L23/53228 ,  H01L23/53238 ,  H01L23/53266 ,  H01L23/5329 ,  H01L23/53295 ,  H01L2221/1047 ,  H01L2924/0002 ,  H01L2924/00

Abstract: An aluminum (Al) layer is formed over a semiconductor substrate. A selective portion of the Al layer is removed to form openings. The Al layer is anodized to obtain an alumina dielectric layer with a plurality of pores substantially perpendicular to a surface of the semiconductor substrate. The openings are filled with a conductive interconnect material. The pores are widened to form air gaps and a top etch stop layer is formed over the alumina dielectric layer.

Abstract translation: 在半导体衬底上形成铝（Al）层。 去除Al层的选择性部分以形成开口。 对Al层进行阳极氧化以获得具有基本垂直于半导体衬底的表面的多个孔的氧化铝介电层。 开口填充有导电互连材料。 孔被加宽以形成气隙，并且在氧化铝介质层上形成顶部蚀刻停止层。

公开(公告)号：US20150179499A1

公开(公告)日：2015-06-25

申请号：US14135785

申请日：2013-12-20

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Tai-I Yang ,  Cheng-Chi Chuang ,  Yung-Chih Wang ,  Tien-Lu Lin

IPC: H01L21/768 ,  H01L23/532 ,  H01L23/528

CPC classification number: H01L23/5283 ,  H01L21/76802 ,  H01L21/76804 ,  H01L21/76807 ,  H01L21/7682 ,  H01L21/76831 ,  H01L21/76834 ,  H01L21/76843 ,  H01L21/76877 ,  H01L21/76879 ,  H01L23/5221 ,  H01L23/5226 ,  H01L23/53238 ,  H01L23/53295 ,  H01L2221/1063 ,  H01L2924/0002 ,  H01L2924/00

Abstract: An interconnect structure includes a first low-k dielectric layer formed over a substrate. A first metal line is disposed in the first low-k dielectric layer. The first metal line includes a first conductive body with a first width and an up landing pad with a second width. The first width is smaller than the second width. The interconnect structure further includes a first air-gap adjacent to sidewalls of the first conductive body. The interconnect structure also includes a second low-k dielectric layer formed over the first low-k dielectric layer and a first via in the second low-k dielectric layer and disposed on the up landing pad.

Abstract translation: 互连结构包括在衬底上形成的第一低k电介质层。 第一金属线设置在第一低k电介质层中。 第一金属线包括具有第一宽度的第一导电体和具有第二宽度的向上着陆垫。 第一宽度小于第二宽度。 互连结构还包括与第一导电体的侧壁相邻的第一气隙。 互连结构还包括形成在第一低k电介质层上的第二低k电介质层和第二低k电介质层中的第一通孔，并设置在上焊垫上。

公开(公告)号：US12051646B2

公开(公告)日：2024-07-30

申请号：US17402897

申请日：2021-08-16

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Hsiang-Lun Kao ,  Hsiang-Wei Liu ,  Tai-I Yang ,  Jian-Hua Chen ,  Yu-Chieh Liao ,  Yung-Chih Wang ,  Tien-Lu Lin

IPC: H01L23/528 ,  H01L21/263 ,  H01L21/311 ,  H01L21/768 ,  H01L23/522 ,  H01L23/532

CPC classification number: H01L23/5283 ,  H01L21/2633 ,  H01L21/31111 ,  H01L21/7682 ,  H01L21/76879 ,  H01L21/76885 ,  H01L23/5222 ,  H01L23/5226 ,  H01L23/528 ,  H01L23/53295 ,  H01L21/76834 ,  H01L2924/0002 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A method comprises forming a first conductive line and a second conductive line in a first dielectric layer over a substrate, each having a planar top surface, applying an etch-back process to the first dielectric layer until a dielectric portion between the first conductive line and the second conductive line has been removed, and the first conductive line and the second conductive line have respective cross sectional shapes including a rounded surface and two rounded corners and depositing a second dielectric layer over the substrate, while leaving a first air gap between the first conductive line and the second conductive line.

公开(公告)号：US20230386911A1

公开(公告)日：2023-11-30

申请号：US18447084

申请日：2023-08-09

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chun-Yuan Chen ,  Shih-Chuan Chiu ,  Jia-Chuan You ,  Chia-Hao Chang ,  Tien-Lu Lin ,  Yu-Ming Lin

IPC: H01L21/768 ,  H01L23/532 ,  H01L21/321 ,  H01L23/522

CPC classification number: H01L21/7684 ,  H01L21/76802 ,  H01L21/76883 ,  H01L21/3212 ,  H01L23/5226 ,  H01L23/53209

Abstract: A method includes forming a first conductive feature on a substrate, forming a via that contacts the first conductive feature, the via comprising a conductive material, performing a Chemical Mechanical Polishing (CMP) process to a top surface of the via, depositing an Interlayer Dielectric (ILD) layer on the via, forming a trench within the ILD layer to expose the via, and filling the trench with a second conductive feature that contacts the via, the second conductive feature comprising a same material as the conductive material.