公开(公告)号：US20160343697A1

公开(公告)日：2016-11-24

申请号：US15223609

申请日：2016-07-29

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Wan-Yu Lee ,  Chun-Hao Tseng ,  Jui Hsieh Lai ,  Tien-Yu Huang ,  Ying-Hao Kuo ,  Kuo-Chung Yee

IPC: H01L25/00 ,  H01L23/31 ,  H01L23/00 ,  H01L25/16 ,  H01L21/768 ,  H01L21/311 ,  H01L23/29 ,  H01L23/538 ,  H01L21/683 ,  H01L21/56

CPC classification number: H01L21/563 ,  H01L21/31111 ,  H01L21/481 ,  H01L21/4857 ,  H01L21/50 ,  H01L21/565 ,  H01L21/568 ,  H01L21/6836 ,  H01L21/76838 ,  H01L23/293 ,  H01L23/3114 ,  H01L23/3171 ,  H01L23/48 ,  H01L23/538 ,  H01L23/5383 ,  H01L23/5389 ,  H01L24/06 ,  H01L24/24 ,  H01L24/82 ,  H01L25/167 ,  H01L25/50 ,  H01L27/14618 ,  H01L31/0232 ,  H01L31/09 ,  H01L2224/24137 ,  H01L2224/24195 ,  H01L2924/10253 ,  H01L2924/1032 ,  H01L2924/1033 ,  H01L2924/1305 ,  H01L2924/13091 ,  H01L2924/00

Abstract: A package for holding a plurality of heterogeneous integrated circuits includes a first chip having a first conductive pad and a first substrate including a first semiconductor, and a second chip having a second conductive pad and a second substrate including a second semiconductor. The second semiconductor is different from the first semiconductor. The package also includes a molding structure in which the first chip and the second chip are embedded, a conductive structure over the first chip and conductively coupled to the first conductive pad and over the second chip and conductively coupled to the second conductive pad, and a passivation layer over the conductive structure. The passivation layer comprises an opening defined therein which exposes a portion of the second chip.