公开(公告)号：US20210057559A1

公开(公告)日：2021-02-25

申请号：US16549266

申请日：2019-08-23

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Li-Yang Chuang ,  Ching-Wei Tsai ,  Wang-Chun Huang ,  Kuan-Lun Cheng

IPC: H01L29/775 ,  H01L23/522 ,  H01L29/06 ,  H01L21/02 ,  H01L21/306 ,  H01L21/311 ,  H01L21/768 ,  H01L29/66

Abstract: An integrated circuit (IC) structure with a nanowire power switch device and a method of forming the IC structure are disclosed. The method includes forming a first layer of metal lines of a first back end of line (BEOL) interconnect structure and forming a semiconductor nanowire structure on a first metal line of the first layer of metal lines. The BEOL interconnect structure is formed on a front end of line (FEOL) device layer having multiple active devices. The method further includes forming a first dielectric layer wrapped around the semiconductor nanowire structure, forming a metal layer on the dielectric layer and on a second metal line of the first layer of metal lines, and forming a second layer of metal lines of a second BEOL interconnect structure on the semiconductor nanowire structure. The first and second metal lines are electrically isolated from each other.

公开(公告)号：US09966469B2

公开(公告)日：2018-05-08

申请号：US15439035

申请日：2017-02-22

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Tung Ying Lee ,  Chien-Chang Su ,  Wang-Chun Huang ,  Yasutoshi Okuno

IPC: H01L21/8242 ,  H01L29/78 ,  H01L21/8234 ,  H01L29/10 ,  H01L21/02 ,  H01L29/165 ,  H01L29/06 ,  H01L21/306 ,  H01L29/66 ,  H01L27/088 ,  H01L21/8238 ,  H01L27/092 ,  H01L29/267 ,  H01L27/146

CPC classification number: H01L29/7851 ,  H01L21/0217 ,  H01L21/02532 ,  H01L21/0262 ,  H01L21/30625 ,  H01L21/823412 ,  H01L21/823431 ,  H01L21/823481 ,  H01L21/823807 ,  H01L21/823821 ,  H01L21/823878 ,  H01L27/0886 ,  H01L27/0924 ,  H01L27/1461 ,  H01L29/0649 ,  H01L29/1054 ,  H01L29/165 ,  H01L29/267 ,  H01L29/66795 ,  H01L29/6681 ,  H01L29/785

Abstract: A method for manufacturing a semiconductor device includes forming a fin structure having a top face and a first side face and a second side face opposite to the first side face, forming a lower cover layer over the first and second side faces, forming an upper cover layer over the first and second side faces, the upper cover layer being spaced apart from the lower cover layer so that exposed regions of the first and second side faces are formed between the lower cover layer and the upper cover layer, and forming first and second semiconductor layers over the exposed regions of the first and second side faces, respectively.

公开(公告)号：US12199095B2

公开(公告)日：2025-01-14

申请号：US17504211

申请日：2021-10-18

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Wang-Chun Huang ,  Chih-Hao Wang ,  Ching-Wei Tsai ,  Kuan-Lun Cheng

IPC: H01L27/088 ,  H01L21/02 ,  H01L21/306 ,  H01L21/308 ,  H01L21/8234 ,  H01L29/06 ,  H01L29/08 ,  H01L29/423 ,  H01L29/66 ,  H01L29/78 ,  H01L29/786

Abstract: The present disclosure describes a structure including a fin field effect transistor (finFET) and a nano-sheet transistor on a substrate and a method of forming the structure. The method can include forming first and second vertical structures over a substrate, where each of the first and the second vertical structures can include a buffer region and a first channel layer formed over the buffer region. The method can further include disposing a masking layer over the first channel layer of the first and second vertical structures, removing a portion of the first vertical structure to form a first recess, forming a second channel layer in the first recess, forming a second recess in the second channel layer, and disposing an insulating layer in the second recess.

公开(公告)号：US11715781B2

公开(公告)日：2023-08-01

申请号：US16802396

申请日：2020-02-26

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Wang-Chun Huang ,  Ching-Wei Tsai ,  Kuan-Lun Cheng ,  Chih-Hao Wang

IPC: H01L29/51 ,  H01L29/423 ,  H01L29/786 ,  H01L29/66 ,  H01L27/088 ,  H01L29/78 ,  H01L21/8234

CPC classification number: H01L29/513 ,  H01L21/823431 ,  H01L27/0886 ,  H01L29/42392 ,  H01L29/66545 ,  H01L29/785 ,  H01L29/78696

Abstract: A semiconductor device includes a substrate, two source/drain (S/D) regions over the substrate, a channel region between the two S/D regions and including a semiconductor material, a deposited capacitor material (DCM) layer over the channel region a dielectric layer over the DCM layer and a metallic gate electrode layer over the dielectric layer.

公开(公告)号：US11152358B2

公开(公告)日：2021-10-19

申请号：US16589888

申请日：2019-10-01

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Wang-Chun Huang ,  Chih-Hao Wang ,  Ching-Wei Tsai ,  Kuan-Lun Cheng

IPC: H01L27/088 ,  H01L29/66 ,  H01L29/423 ,  H01L29/78 ,  H01L29/08 ,  H01L29/786 ,  H01L21/8234 ,  H01L21/02 ,  H01L21/308 ,  H01L21/306 ,  H01L29/06

Abstract: The present disclosure describes a method to form a fin field effect transistor (finFET) and a nano-sheet transistor on a substrate. The method can include forming first and second vertical structures over a substrate, where each of the first and the second vertical structures can include a buffer region and a first channel layer formed over the buffer region. The method can further include disposing a masking layer over the first channel layer of the first and second vertical structures, removing a portion of the first vertical structure to form a first recess, forming a second channel layer in the first recess, forming a second recess in the second channel layer, and disposing an insulating layer in the second recess.

公开(公告)号：US10971609B2

公开(公告)日：2021-04-06

申请号：US16549266

申请日：2019-08-23

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Li-Yang Chuang ,  Ching-Wei Tsai ,  Wang-Chun Huang ,  Kuan-Lun Cheng

IPC: H01L29/775 ,  H01L23/522 ,  H01L29/06 ,  H01L21/02 ,  H01L29/66 ,  H01L21/306 ,  H01L21/311 ,  H01L21/768

Abstract: An integrated circuit (IC) structure with a nanowire power switch device and a method of forming the IC structure are disclosed. The method includes forming a first layer of metal lines of a first back end of line (BEOL) interconnect structure and forming a semiconductor nanowire structure on a first metal line of the first layer of metal lines. The BEOL interconnect structure is formed on a front end of line (FEOL) device layer having multiple active devices. The method further includes forming a first dielectric layer wrapped around the semiconductor nanowire structure, forming a metal layer on the dielectric layer and on a second metal line of the first layer of metal lines, and forming a second layer of metal lines of a second BEOL interconnect structure on the semiconductor nanowire structure. The first and second metal lines are electrically isolated from each other.

公开(公告)号：US10326023B2

公开(公告)日：2019-06-18

申请号：US15972961

申请日：2018-05-07

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Tung Ying Lee ,  Chien-Chang Su ,  Wang-Chun Huang ,  Yasutoshi Okuno

IPC: H01L29/165 ,  H01L21/306 ,  H01L29/78 ,  H01L29/10 ,  H01L29/66 ,  H01L21/02 ,  H01L21/8234 ,  H01L21/8238 ,  H01L27/088 ,  H01L27/092 ,  H01L29/06 ,  H01L27/146 ,  H01L29/267

Abstract: A method for manufacturing a semiconductor device includes forming a fin structure having a top face and a first side face and a second side face opposite to the first side face, forming a lower cover layer over the first and second side faces, forming an upper cover layer over the first and second side faces, the upper cover layer being spaced apart from the lower cover layer so that exposed regions of the first and second side faces are formed between the lower cover layer and the upper cover layer, and forming first and second semiconductor layers over the exposed regions of the first and second side faces, respectively.

公开(公告)号：US09601626B2

公开(公告)日：2017-03-21

申请号：US14604537

申请日：2015-01-23

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Tung Ying Lee ,  Yasutoshi Okuno ,  Chien-Chang Su ,  Wang-Chun Huang

IPC: H01L27/088 ,  H01L29/78 ,  H01L29/165 ,  H01L29/10 ,  H01L29/66 ,  H01L21/02

CPC classification number: H01L29/7851 ,  H01L21/0217 ,  H01L21/02532 ,  H01L21/0262 ,  H01L21/30625 ,  H01L21/823412 ,  H01L21/823431 ,  H01L21/823481 ,  H01L21/823807 ,  H01L21/823821 ,  H01L21/823878 ,  H01L27/0886 ,  H01L27/0924 ,  H01L27/1461 ,  H01L29/0649 ,  H01L29/1054 ,  H01L29/165 ,  H01L29/267 ,  H01L29/66795 ,  H01L29/6681 ,  H01L29/785

Abstract: A semiconductor device includes a fin structure protruding from a substrate and having a top face and a first side face and a second side face opposite to the first side face, and first semiconductor layers disposed over the first and second side faces of the fin structure. A thickness in a vertical direction of the first semiconductor layers is smaller than a height of the fin structure.