公开(公告)号：US20190131293A1

公开(公告)日：2019-05-02

申请号：US16219747

申请日：2018-12-13

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Wun-Jie Lin ,  Han-Jen Yang ,  Yu-Ti Su

IPC: H01L27/02 ,  H01L21/28 ,  H01L23/60 ,  H01L21/8234 ,  H01L29/10 ,  H01L27/088 ,  H02H9/04 ,  H01L29/66

Abstract: An Electro-Static Discharge (ESD) includes a first well having a first conductivity type on a substrate. The device further includes a second well within the first well. The second well has a second conductivity type. The device further includes a third well within the first well. The third well has the second conductivity type. The device further includes a first gate device disposed over the first well, a plurality of active regions between the first gate device and the dummy gate, and a dummy gate disposed within a space between the active regions. The dummy gate is positioned over a space between the second and third wells.

公开(公告)号：US12033962B2

公开(公告)日：2024-07-09

申请号：US18232739

申请日：2023-08-10

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Tao-Yi Hung ,  Wun-Jie Lin ,  Jam-Wem Lee ,  Kuo-Ji Chen

IPC: H01L23/60 ,  H01L27/02 ,  H02H9/04

CPC classification number: H01L23/60 ,  H01L27/0266 ,  H01L27/0292 ,  H02H9/046

Abstract: An electrostatic discharge (ESD) protection apparatus and method for fabricating the same are disclosed herein. In some embodiments, the ESD protection apparatus comprises: an internal circuit formed in a first wafer; an array of electrostatic discharge (ESD) circuits formed in a second wafer, wherein the ESD circuits include a plurality of ESD protection devices each coupled to a corresponding switch and configured to protect the internal circuit from a transient ESD event; and a switch controller in the second wafer, wherein the switch controller is configured to control, based on a control signal from the first wafer, each of the plurality of ESD protection devices to be activated or deactivated by the corresponding switch, and wherein the first wafer is bonded to the second wafer.

公开(公告)号：US11817403B2

公开(公告)日：2023-11-14

申请号：US17199299

申请日：2021-03-11

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Tao-Yi Hung ,  Wun-Jie Lin ,  Jam-Wem Lee ,  Kuo-Ji Chen

IPC: H01L23/60 ,  H01L27/02 ,  H02H9/04

CPC classification number: H01L23/60 ,  H01L27/0266 ,  H01L27/0292 ,  H02H9/046

Abstract: An electrostatic discharge (ESD) protection apparatus and method for fabricating the same are disclosed herein. In some embodiments, the ESD protection apparatus comprises: an internal circuit formed in a first wafer; an array of electrostatic discharge (ESD) circuits formed in a second wafer, wherein the ESD circuits include a plurality of ESD protection devices each coupled to a corresponding switch and configured to protect the internal circuit from a transient ESD event; and a switch controller in the second wafer, wherein the switch controller is configured to control, based on a control signal from the first wafer, each of the plurality of ESD protection devices to be activated or deactivated by the corresponding switch, and wherein the first wafer is bonded to the second wafer.

公开(公告)号：US11728330B2

公开(公告)日：2023-08-15

申请号：US17219495

申请日：2021-03-31

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Yu-Hung Yeh ,  Wun-Jie Lin ,  Jam-Wem Lee

IPC: H01L27/02 ,  H01L23/522 ,  H01L23/535 ,  H02H9/04

CPC classification number: H01L27/0288 ,  H01L23/5223 ,  H01L23/5228 ,  H01L23/535 ,  H01L27/0285 ,  H01L27/0292 ,  H02H9/046

Abstract: An electrostatic discharge (ESD) protection apparatus and method for fabricating the same are disclosed herein. In some embodiments, the ESD protection apparatus, comprises: a plurality of transistors patterned on a semiconductor substrate during a front-end-of-line (FEOL) process, metal interconnects formed on top of the plurality of transistors during a back-end-of-line (BEOL) process and configured to interconnect the plurality of transistors, and a plurality of passive components formed under the semiconductor substrate in a backside layer during a backside a back-end-of-line (B-BEOL) process, wherein the plurality of passive components are connected to the plurality of transistors through a plurality of vias.

公开(公告)号：US10475793B2

公开(公告)日：2019-11-12

申请号：US15495106

申请日：2017-04-24

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chien-Yao Huang ,  Wun-Jie Lin ,  Chia-Wei Hsu ,  Yu-Ti Su

IPC: H01L27/092 ,  H01L29/06 ,  H01L29/08 ,  H01L29/94 ,  H01L27/02 ,  H01L27/08 ,  H01L29/861

Abstract: A capacitor cell is provided. A first PMOS transistor is coupled between a power supply and a first node, having a gate coupled to a second node. A first NMOS transistor coupled between a ground and the second node, having a gate coupled to the first node. A second PMOS transistor, having a drain coupled to the second node, a gate coupled to the second node, and a source coupled to the power supply or the first node. A second NMOS transistor, having a drain coupled to the first node, a gate coupled to the first node, and a source coupled to the ground or the second node.

公开(公告)号：US20220293534A1

公开(公告)日：2022-09-15

申请号：US17199299

申请日：2021-03-11

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Tao-Yi Hung ,  Wun-Jie Lin ,  Jam-Wem Lee ,  Kuo-Ji Chen

IPC: H01L23/60 ,  H02H9/04 ,  H01L27/02

Abstract: An electrostatic discharge (ESD) protection apparatus and method for fabricating the same are disclosed herein. In some embodiments, the ESD protection apparatus comprises: an internal circuit formed in a first wafer; an array of electrostatic discharge (ESD) circuits formed in a second wafer, wherein the ESD circuits include a plurality of ESD protection devices each coupled to a corresponding switch and configured to protect the internal circuit from a transient ESD event; and a switch controller in the second wafer, wherein the switch controller is configured to control, based on a control signal from the first wafer, each of the plurality of ESD protection devices to be activated or deactivated by the corresponding switch, and wherein the first wafer is bonded to the second wafer.

公开(公告)号：US20210082907A1

公开(公告)日：2021-03-18

申请号：US17107694

申请日：2020-11-30

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Wun-Jie Lin ,  Han-Jen Yang ,  Yu-Ti Su

IPC: H01L27/02 ,  H02H9/04 ,  H01L27/088 ,  H01L29/10 ,  H01L21/8234 ,  H01L29/66 ,  H01L23/60 ,  H01L21/28

Abstract: An Electro-Static Discharge (ESD) includes a first well having a first conductivity type on a substrate. The device further includes a second well within the first well. The second well has a second conductivity type. The device further includes a third well within the first well. The third well has the second conductivity type. The device further includes a first gate device disposed over the first well, a plurality of active regions between the first gate device and the dummy gate, and a dummy gate disposed within a space between the active regions. The dummy gate is positioned over a space between the second and third wells.

公开(公告)号：US10157905B2

公开(公告)日：2018-12-18

申请号：US15670356

申请日：2017-08-07

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Wun-Jie Lin ,  Han-Jen Yang ,  Yu-Ti Su

IPC: H01L29/66 ,  H01L27/02 ,  H01L21/28 ,  H02H9/04 ,  H01L27/088 ,  H01L29/10 ,  H01L21/8234 ,  H01L23/60

Abstract: An integrated circuit device includes at least two epitaxially grown active regions grown onto a substrate, the active regions being placed between a first gate device and a second gate device. The integrated circuit device includes at least one dummy gate between the two epitaxially grown active regions and between the first gate device and the second gate device, wherein each active region is substantially uniform in length. The first gate device and the second device are formed over a first well having a first conductivity type and the dummy gate is formed over a second well having a second conductivity type.