公开(公告)号：US20220262635A1

公开(公告)日：2022-08-18

申请号：US17736505

申请日：2022-05-04

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Tzu-Ang Chao ,  Gregory Michael Pitner ,  Tse-An Chen ,  Lain-Jong Li ,  Yu Chao Lin

IPC: H01L21/02 ,  H01L29/06 ,  H01L51/00 ,  H01L29/78 ,  H01L29/423 ,  H01L29/40 ,  H01L29/66 ,  H01L51/05 ,  H01L51/56 ,  H01L51/10 ,  H01L29/786

Abstract: A semiconductor device and method of manufacturing using carbon nanotubes are provided. In embodiments a stack of nanotubes are formed and then a non-destructive removal process is utilized to reduce the thickness of the stack of nanotubes. A device such as a transistor may then be formed from the reduced stack of nanotubes.

公开(公告)号：US20210305508A1

公开(公告)日：2021-09-30

申请号：US17072897

申请日：2020-10-16

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Tung Ying Lee ,  Shao-Ming Yu ,  Yu Chao Lin

IPC: H01L45/00 ,  H01L27/24

Abstract: In an embodiment, a device includes: a first metallization layer over a substrate, the substrate including active devices; a first bit line over the first metallization layer, the first bit line connected to first interconnects of the first metallization layer, the first bit line extending in a first direction, the first direction parallel to gates of the active devices; a first phase-change random access memory (PCRAM) cell over the first bit line; a word line over the first PCRAM cell, the word line extending in a second direction, the second direction perpendicular to the gates of the active devices; and a second metallization layer over the word line, the word line connected to second interconnects of the second metallization layer.

公开(公告)号：US20210358750A1

公开(公告)日：2021-11-18

申请号：US17071554

申请日：2020-10-15

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Tzu-Ang Chao ,  Gregory Michael Pitner ,  Tse-An Chen ,  Lain-Jong Li ,  Yu Chao Lin

IPC: H01L21/02 ,  H01L51/00 ,  H01L29/06

Abstract: A semiconductor device and method of manufacturing using carbon nanotubes are provided. In embodiments a stack of nanotubes are formed and then a non-destructive removal process is utilized to reduced the thickness of the stack of nanotubes. A device such as a transistor may then be formed from the reduced stack of nanotubes.

公开(公告)号：US20210336138A1

公开(公告)日：2021-10-28

申请号：US16992210

申请日：2020-08-13

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Tung Ying Lee ,  Yu Chao Lin ,  Shao-Ming Yu

IPC: H01L45/00

Abstract: A method includes forming a dielectric layer over a substrate, the dielectric layer having a top surface; etching an opening in the dielectric layer; forming a bottom electrode within the opening, the bottom electrode including a barrier layer; forming a phase-change material (PCM) layer within the opening and on the bottom electrode, wherein a top surface of the PCM layer is level with or below the top surface of the dielectric layer; and forming a top electrode on the PCM layer.

公开(公告)号：US10862031B2

公开(公告)日：2020-12-08

申请号：US16289733

申请日：2019-03-01

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Yu Chao Lin ,  Jui-Ming Chen ,  Shao-Ming Yu ,  Tung Ying Lee ,  Yu-Sheng Chen

IPC: H01L45/00 ,  H01L27/24

Abstract: In some embodiments, the present disclosure relates to an integrated chip including a phase change material disposed over a bottom electrode and configured to change from a crystalline structure to an amorphous structure upon temperature changes. A top electrode is disposed over an upper surface of the phase change material. A via electrically contacts a top surface of the top electrode. Further, a maximum width of the upper surface of the phase change material is less than a maximum width of a bottom surface of the phase change material.

公开(公告)号：US20170194147A1

公开(公告)日：2017-07-06

申请号：US15096541

申请日：2016-04-12

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Yu Chao Lin ,  Chao-Cheng Chen ,  Chun-Hung Lee ,  Yu-Lung Yang

IPC: H01L21/033

CPC classification number: H01L21/0338 ,  H01L21/02326 ,  H01L21/0234 ,  H01L21/0335 ,  H01L21/0337 ,  H01L21/30655 ,  H01L21/3086 ,  H01L21/31116 ,  H01L21/31144 ,  H01L21/32139

Abstract: An integrated circuit manufacturing method includes forming mandrel patterns over a patterning layer of a substrate; and forming a spacer layer over the patterning layer, over the mandrel patterns, and onto sidewalls of the mandrel patterns. The method further includes trimming the spacer layer using a dry etching technique such that a space between adjacent sidewalls of the spacer layer substantially matches a dimension of the mandrel patterns along a pattern width direction. The method further includes etching the spacer layer to expose the mandrel patterns and the patterning layer, resulting in a patterned spacer layer on the sidewalls of the mandrel patterns. After the trimming of the spacer layer and the etching of the spacer layer, the method further includes removing the mandrel patterns. The method further includes transferring a pattern of the patterned spacer layer to the patterning layer.

公开(公告)号：US20240390861A1

公开(公告)日：2024-11-28

申请号：US18789443

申请日：2024-07-30

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Tzu-Ang Chao ,  Gregory Michael Pitner ,  Tse-An Chen ,  Lain-Jong Li ,  Yu Chao Lin

IPC: B01D67/00 ,  H01L21/02 ,  H01L29/06 ,  H01L29/40 ,  H01L29/423 ,  H01L29/66 ,  H01L29/78 ,  H01L29/786 ,  H10K10/46 ,  H10K10/84 ,  H10K71/00 ,  H10K71/12 ,  H10K85/20

Abstract: A semiconductor device and method of manufacturing using carbon nanotubes are provided. In embodiments a stack of nanotubes are formed and then a non-destructive removal process is utilized to reduce the thickness of the stack of nanotubes. A device such as a transistor may then be formed from the reduced stack of nanotubes.

公开(公告)号：US12151213B2

公开(公告)日：2024-11-26

申请号：US18356636

申请日：2023-07-21

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Tzu-Ang Chao ,  Gregory Michael Pitner ,  Tse-An Chen ,  Lain-Jong Li ,  Yu Chao Lin

IPC: H01L21/02 ,  B01D67/00 ,  H01L29/06 ,  H01L29/40 ,  H01L29/423 ,  H01L29/66 ,  H01L29/78 ,  H01L29/786 ,  H10K10/46 ,  H10K10/84 ,  H10K71/00 ,  H10K71/12 ,  H10K85/20

Abstract: A semiconductor device and method of manufacturing using carbon nanotubes are provided. In embodiments a stack of nanotubes are formed and then a non-destructive removal process is utilized to reduce the thickness of the stack of nanotubes. A device such as a transistor may then be formed from the reduced stack of nanotubes.

公开(公告)号：US20240276892A1

公开(公告)日：2024-08-15

申请号：US18643497

申请日：2024-04-23

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Tung Ying Lee ,  Shao-Ming Yu ,  Yu Chao Lin

IPC: H10N70/00 ,  H10B63/00 ,  H10N70/20

CPC classification number: H10N70/068 ,  H10B63/24 ,  H10B63/80 ,  H10N70/063 ,  H10N70/231 ,  H10N70/826

Abstract: In an embodiment, a device includes: a first metallization layer over a substrate, the substrate including active devices; a first bit line over the first metallization layer, the first bit line connected to first interconnects of the first metallization layer, the first bit line extending in a first direction, the first direction parallel to gates of the active devices; a first phase-change random access memory (PCRAM) cell over the first bit line; a word line over the first PCRAM cell, the word line extending in a second direction, the second direction perpendicular to the gates of the active devices; and a second metallization layer over the word line, the word line connected to second interconnects of the second metallization layer.

公开(公告)号：US11997933B2

公开(公告)日：2024-05-28

申请号：US17867460

申请日：2022-07-18

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Tung Ying Lee ,  Shao-Ming Yu ,  Yu Chao Lin

IPC: H10N70/00 ,  H10B63/00 ,  H10N70/20

CPC classification number: H10N70/068 ,  H10B63/24 ,  H10B63/80 ,  H10N70/063 ,  H10N70/231 ,  H10N70/826

Abstract: In an embodiment, a device includes: a first metallization layer over a substrate, the substrate including active devices; a first bit line over the first metallization layer, the first bit line connected to first interconnects of the first metallization layer, the first bit line extending in a first direction, the first direction parallel to gates of the active devices; a first phase-change random access memory (PCRAM) cell over the first bit line; a word line over the first PCRAM cell, the word line extending in a second direction, the second direction perpendicular to the gates of the active devices; and a second metallization layer over the word line, the word line connected to second interconnects of the second metallization layer.