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    ETCHING TO REDUCE LINE WIGGLING
    11.
    发明申请
    ETCHING TO REDUCE LINE WIGGLING 有权

    公开(公告)号：US20220148918A1

    公开(公告)日：2022-05-12

    申请号：US17586412

    申请日：2022-01-27

    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

    Inventor： Kuan-Wei Huang ,  Cheng-Li Fan ,  Yu-Yu Chen

    IPC: H01L21/768 ,  H01L23/535 ,  H01L21/033 ,  H01L23/522 ,  H01L23/532 ,  H01L21/311

    Abstract: A method for reducing wiggling in a line includes forming a first patterning layer over a metal feature and depositing a first mask layer over the first patterning layer. The first mask layer is patterned to form a first set of one or more openings therein and then thinned. The pattern of the first mask layer is transferred to the first patterning layer to form a second set of one or more openings therein. The first patterning layer is etched to widen the second set of one or more openings. The first patterning layer may be comprised of silicon or an oxide material. The openings in the first patterning layer may be widened while a mask layer is over the first patterning layer.

    LITHOGRAPHY METHOD TO REDUCE SPACING BETWEEN INTERCONNECT WIRES IN INTERCONNECT STRUCTURE
    12.
    发明申请
    LITHOGRAPHY METHOD TO REDUCE SPACING BETWEEN INTERCONNECT WIRES IN INTERCONNECT STRUCTURE 有权

    公开(公告)号：US20220093455A1

    公开(公告)日：2022-03-24

    申请号：US17126246

    申请日：2020-12-18

    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

    Inventor： Yi-Nien Su ,  Yu-Yu Chen

    IPC: H01L21/768 ,  H01L21/033

    Abstract: In some embodiments, the present disclosure relates to a method that includes depositing multiple hard mask layers over an interconnect dielectric layer. A first patterning layer is deposited over the multiple hard mask layers, and a first masking structure is formed over the first masking structure. The first masking structure has openings formed by a first extreme ultraviolet (EUV) lithography process. Portions of the first patterning layer are removed according to the first masking structure. A second masking structure is formed within the patterned first patterning layer. A third masking structure is formed over a topmost one of the hard mask layers and has openings formed by a second EUV lithography process. Removal processes are performed to pattern the multiple hard mask layers to form openings in the interconnect dielectric layer, and interconnect wires having rounded corners are formed within the openings of the interconnect dielectric layer.

    Etching and Structures Formed Thereby
    15.
    发明申请
    Etching and Structures Formed Thereby 审中-公开

    公开(公告)号：US20190148159A1

    公开(公告)日：2019-05-16

    申请号：US16203955

    申请日：2018-11-29

    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

    Inventor： Kuan-Wei Huang ,  Yu-Yu Chen ,  Chia-Nan Lin

    IPC: H01L21/306 ,  H01L21/67 ,  H01L21/3065

    Abstract: Embodiments described herein relate generally to methods for etching structures and the structures formed thereby. In some embodiments, an etch selectivity between a first portion of a material and a second portion of the material is increased. Increasing the etch selectivity includes performing an anisotropic treatment, such as an anisotropic ion implantation, on the material to treat the first portion of the material, and the second portion of the material remains untreated after the anisotropic treatment. After increasing the etch selectivity, the first portion of the material is etched. The etching may be a wet or dry etch, and may further be isotropic or anisotropic.

    ETCHING AND STRUCTURES FORMED THEREBY
    16.
    发明申请
    ETCHING AND STRUCTURES FORMED THEREBY 审中-公开

    公开(公告)号：US20190148158A1

    公开(公告)日：2019-05-16

    申请号：US15814082

    申请日：2017-11-15

    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

    Inventor： Kuan-Wei Huang ,  Yu-Yu Chen ,  Chia-Nan Lin

    IPC: H01L21/306 ,  H01L21/67 ,  H01L21/3065

    Abstract: Embodiments described herein relate generally to methods for etching structures and the structures formed thereby. In some embodiments, an etch selectivity between a first portion of a material and a second portion of the material is increased. Increasing the etch selectivity includes performing an anisotropic treatment, such as an anisotropic ion implantation, on the material to treat the first portion of the material, and the second portion of the material remains untreated after the anisotropic treatment. After increasing the etch selectivity, the first portion of the material is etched. The etching may be a wet or dry etch, and may further be isotropic or anisotropic.

    Etching and structures formed thereby
    17.
    发明授权
    Etching and structures formed thereby 有权

    公开(公告)号：US10269576B1

    公开(公告)日：2019-04-23

    申请号：US15814082

    申请日：2017-11-15

    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

    Inventor： Kuan-Wei Huang ,  Yu-Yu Chen ,  Chia-Nan Lin

    IPC: H01L21/461 ,  H01L21/306 ,  H01L21/67 ,  H01L21/3065 ,  H01L21/02 ,  H01L21/3105 ,  H01L21/311

    Abstract: Embodiments described herein relate generally to methods for etching structures and the structures formed thereby. In some embodiments, an etch selectivity between a first portion of a material and a second portion of the material is increased. Increasing the etch selectivity includes performing an anisotropic treatment, such as an anisotropic ion implantation, on the material to treat the first portion of the material, and the second portion of the material remains untreated after the anisotropic treatment. After increasing the etch selectivity, the first portion of the material is etched. The etching may be a wet or dry etch, and may further be isotropic or anisotropic.

    Semiconductor device and manufacturing method thereof
    18.
    发明授权
    Semiconductor device and manufacturing method thereof 有权

    公开(公告)号：US10157776B2

    公开(公告)日：2018-12-18

    申请号：US15800444

    申请日：2017-11-01

    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

    Inventor： Yan-Jhi Huang ,  Yu-Yu Chen

    IPC: H01L21/768 ,  H01L21/033

    Abstract: A method for manufacturing a semiconductor device includes forming a hard mask layer overlying a device layer of a semiconductor device, a mandrel underlayer over hard mask layer, and a mandrel layer over mandrel underlayer. The mandrel layer has a plurality of mandrel lines extending along a first direction. A plurality of openings are formed in mandrel underlayer extending in a second direction substantially perpendicular to first direction. A spacer layer is formed over mandrel underlayer and layer. Spacer layer fills plurality of openings in underlayer. Portions of spacer layer are removed to expose an upper surface of underlayer and mandrel layer, and mandrel layer is removed. By using remaining portions of spacer layer as a mask, underlayer and hard mask layer are removed, to form a hard mask pattern with first hard mask pattern lines extending along first direction and second hard mask pattern lines extending along second direction.

    Self-Aligned Double Patterning
    20.
    发明申请
    Self-Aligned Double Patterning 有权

    公开(公告)号：US20220384201A1

    公开(公告)日：2022-12-01

    申请号：US17883930

    申请日：2022-08-09

    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

    Inventor： Kuan-Wei Huang ,  Yu-Yu Chen ,  Jyu-Horng Shieh

    IPC: H01L21/308 ,  H01L21/768 ,  H01L21/311

    Abstract: A method includes patterning a mandrel layer over a target layer to form first mandrels and second mandrels, the first mandrels having a larger width than the second mandrels. A spacer layer is formed over the first mandrels and the second mandrels, and altered so that a thickness of the spacer layer over the first mandrels is greater than a thickness of the spacer layer over the second mandrels. Spacers are formed from the spacer layer which have a greater width adjacent the first mandrels than the spacers which are adjacent the second mandrels. The spacers are used to etch a target layer.

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