公开(公告)号：US20210297068A1

公开(公告)日：2021-09-23

申请号：US17339121

申请日：2021-06-04

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Chi-Lin Liu ,  Ting-Wei Chiang ,  Jerry Chang-Jui Kao ,  Hui-Zhong Zhuang ,  Lee-Chung Lu ,  Shang-Chih Hsieh ,  Che Min Huang

IPC: H03K3/3562 ,  G01R31/3185 ,  H01L27/092

Abstract: In some embodiments, a flip-flop is disposed as an integrated circuit layout on a flip-flop region of a semiconductor substrate. The flip-flop includes a first clock inverter circuit that resides within the flip-flop region, and a second clock inverter circuit residing within the flip-flop region. The first clock inverter circuit and the second clock inverter circuit are disposed on a first line. Master switch circuitry is made up of a first plurality of devices which are circumscribed by a master switch perimeter that resides within the flip-flop region of the integrated circuit layout. The master switch circuitry and the first clock inverter circuit are disposed on a second line perpendicular to the first line. Slave switch circuitry is operably coupled to an output of the master switch circuitry. The slave switch circuitry is made up of a third plurality of devices that are circumscribed by a slave switch perimeter. The slave switch circuitry and the second clock inverter circuit are disposed on a third line that is in parallel with and spaced apart from the second line.

公开(公告)号：US10382018B2

公开(公告)日：2019-08-13

申请号：US15443504

申请日：2017-02-27

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

Inventor： Chi-Lin Liu ,  Shang-Chih Hsieh ,  Lee-Chung Lu ,  Chang-Yu Wu

IPC: H03K3/356 ,  G01R31/3185 ,  H03K3/037

Abstract: A flip-flop circuit includes a first latch, a second latch and a trigger circuit. The first latch is configured to set a first output signal based on a first input signal and a clock signal. The second latch is configured to set a second output signal based on a second input signal and the clock signal. The trigger circuit is coupled with the first latch and the second latch. The trigger circuit is configured to generate the second input signal based on at least the second output signal. The trigger circuit is configured to cause the second input signal to have different voltage swings based on the first output signal and the second output signal. The trigger circuit includes a logic circuit coupled to at least the first latch or the second latch. The logic circuit is configured to output the second output signal.

公开(公告)号：US20240037309A1

公开(公告)日：2024-02-01

申请号：US18345389

申请日：2023-06-30

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Chi-Lin Liu ,  Shang-Chih Hsieh ,  Jian-Sing Li ,  Wei-Hsiang Ma ,  Yi-Hsun Chen ,  Cheok-Kei Lei

IPC: G06F30/392 ,  G06F30/347 ,  G06F30/39 ,  H01L27/02

CPC classification number: G06F30/392 ,  G06F30/347 ,  G06F30/39 ,  H01L27/0207

Abstract: A multiplexer circuit includes first and second fins each extending in an X-axis direction. First, second, third and fourth gates extend in a Y-axis direction perpendicular to the X-axis direction and contact the first and second fins. The first, second, third and fourth gates are configured to receive first, second, third and fourth data signals, respectively. Fifth, sixth, seventh and eighth gates extend in the Y-axis direction and contact the first and second fins, the fifth, sixth, seventh and eighth gates, and are configured to receive the first, second, third and fourth select signals, respectively. An input logic circuit is configured to provide an output at an intermediate node. A ninth gate extends in the Y-axis direction and contacts the first and second fins. An output logic circuit is configured to provide a selected one of the first, second, third and fourth data signals at an output terminal.

公开(公告)号：US20210200927A1

公开(公告)日：2021-07-01

申请号：US16732206

申请日：2019-12-31

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Cheok-Kei Lei ,  Chi-Lin Liu ,  Yu-Lun Ou ,  Chien-Hsing Li ,  Zhe-Wei Jiang ,  Hui-Zhong Zhuang

IPC: G06F30/392 ,  H01L27/02 ,  H01L23/528 ,  G06F30/327

Abstract: A system and method for transistor placement in a standard cell layout includes identifying a plurality of transistors in a circuit. A drain terminal of each of the plurality of transistors is connected to an output of the circuit. The system and method also include determining that a first transistor and a second transistor of the plurality of transistors satisfy a merging priority, combining an active region of the first transistor and the second transistor to form a mega transistor having a common active region, and replacing the first transistor and the second transistor in the standard cell layout of the circuit with the mega transistor. The common active region combines the active region of a first drain terminal of the first transistor and a second drain terminal of the second transistor.

公开(公告)号：US10943050B2

公开(公告)日：2021-03-09

申请号：US16514210

申请日：2019-07-17

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

Inventor： Cheok-Kei Lei ,  Jerry Chang Jui Kao ,  Chi-Lin Liu ,  Hui-Zhong Zhuang ,  Zhe-Wei Jiang ,  Chien-Hsing Li

IPC: G06F30/398 ,  G06F30/392 ,  G06F30/367

Abstract: A method of making an integrated circuit includes operations to identify reverse signal nets of the circuit layout, determine when the conductive lines to the reverse signal net have parasitic capacitance, and determine how to adjust an integrated circuit layout to reduce the parasitic capacitance of the conductive lines to the reverse signal net. The method further includes an operation to determine whether to move one of the conductive lines in the integrated circuit layout, and an operation to determine whether to insert an isolation structure between the conductive lines of the reverse signal net having parasitic capacitance.

公开(公告)号：US10664565B2

公开(公告)日：2020-05-26

申请号：US15936712

申请日：2018-03-27

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

Inventor： Chi-Lin Liu ,  Sheng-Hsiung Chen ,  Jerry Chang-Jui Kao ,  Fong-Yuan Chang ,  Lee-Chung Lu ,  Shang-Chih Hsieh ,  Wei-Hsiang Ma

IPC: G06F17/50

Abstract: A method (of expanding a set of standard cells which comprise a library, the library being stored on a non-transitory computer-readable medium) includes: selecting one ad hoc group amongst ad hoc groups of elementary standard cells which are recurrent resulting in a selected group such that the elementary standard cells in the selected group having connections so as to represent a corresponding logic circuit, each elementary standard cell representing a logic gate, and the selected group corresponding providing a selected logical function which is representable correspondingly as a selected Boolean expression; generating, in correspondence to the selected group, one or more macro standard cells; and adding the one or more macro standard cells to, and thereby expanding, the set of standard cells; and wherein at least one aspect of the method is executed by a processor of a computer.

公开(公告)号：US09584099B2

公开(公告)日：2017-02-28

申请号：US14539407

申请日：2014-11-12

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

Inventor： Chi-Lin Liu ,  Shang-Chih Hsieh ,  Lee-Chung Lu ,  Chang-Yu Wu

IPC: H03K3/356 ,  H03K3/037 ,  G01R31/3185

CPC classification number: H03K3/356104 ,  G01R31/318541 ,  H03K3/037 ,  H03K3/356121

Abstract: A flip-flop circuit includes a first latch, a second latch, and a trigger stage. The first latch is configured to set a first latch output signal based on a first latch input signal and a clock signal. The second latch is configured to set a second latch output signal based on a second latch input signal and the clock signal. The trigger stage is configured to generate the second latch input signal based on the first latch output signal. The trigger stage is configured to cause the second input signal to have different voltage swings based on the first latch output signal and the second latch output signal.

Abstract translation: 触发器电路包括第一锁存器，第二锁存器和触发器级。 第一锁存器被配置为基于第一锁存器输入信号和时钟信号来设置第一锁存器输出信号。 第二锁存器被配置为基于第二锁存器输入信号和时钟信号来设置第二锁存器输出信号。 触发级被配置为基于第一锁存器输出信号产生第二锁存器输入信号。 触发级被配置为基于第一锁存器输出信号和第二锁存器输出信号使第二输入信号具有不同的电压摆幅。

公开(公告)号：US12190034B2

公开(公告)日：2025-01-07

申请号：US18362938

申请日：2023-07-31

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

Inventor： Chi-Lin Liu ,  Jerry Chang-Jui Kao ,  Wei-Hsiang Ma ,  Lee-Chung Lu ,  Fong-Yuan Chang ,  Sheng-Hsiung Chen ,  Shang-Chih Hsieh

IPC: G06F30/327 ,  G06F111/06 ,  G06F119/18

Abstract: A logic circuit (for providing a multibit flip-flop (MBFF) function) includes: a first inverter to receive a clock signal and generate a corresponding clock_bar signal; a second inverter to receive the clock_bar signal and generate a corresponding clock_bar_bar signal; a third inverter to receive a control signal and generate a corresponding control_bar signal; and a series-chain of 1-bit transfer flip-flop (TXFF) circuits, each including: a NAND circuit to receive data signals; and a 1-bit transmit gate flip-flop (TGFF) circuit to output signals Q and q, and receive an output of the NAND circuit, the signal q from the TGFF circuit of a preceding TXFF circuit in the series-chain, the clock_bar and clock_bar_bar signals, and the control and control_bar signals; and the first transfer TXFF circuit in the series-chain being configured to receive a start signal in place of the signal q from an otherwise preceding TGFF circuit.

公开(公告)号：US12147750B2

公开(公告)日：2024-11-19

申请号：US18345389

申请日：2023-06-30

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Chi-Lin Liu ,  Shang-Chih Hsieh ,  Jian-Sing Li ,  Wei-Hsiang Ma ,  Yi-Hsun Chen ,  Cheok-Kei Lei

IPC: G06F30/30 ,  G06F30/347 ,  G06F30/39 ,  G06F30/392 ,  H01L27/02

Abstract: A multiplexer circuit includes first and second fins each extending in an X-axis direction. First, second, third and fourth gates extend in a Y-axis direction perpendicular to the X-axis direction and contact the first and second fins. The first, second, third and fourth gates are configured to receive first, second, third and fourth data signals, respectively. Fifth, sixth, seventh and eighth gates extend in the Y-axis direction and contact the first and second fins, the fifth, sixth, seventh and eighth gates, and are configured to receive the first, second, third and fourth select signals, respectively. An input logic circuit is configured to provide an output at an intermediate node. A ninth gate extends in the Y-axis direction and contacts the first and second fins. An output logic circuit is configured to provide a selected one of the first, second, third and fourth data signals at an output terminal.

公开(公告)号：US11755798B2

公开(公告)日：2023-09-12

申请号：US17340662

申请日：2021-06-07

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

Inventor： Chi-Lin Liu ,  Jerry Chang-Jui Kao ,  Wei-Hsiang Ma ,  Lee-Chung Lu ,  Fong-Yuan Chang ,  Sheng-Hsiung Chen ,  Shang-Chih Hsieh

IPC: G06F30/327 ,  G06F111/06 ,  G06F119/18

CPC classification number: G06F30/327 ,  G06F2111/06 ,  G06F2119/18

Abstract: A logic circuit including first and second inverters, first and second NAND circuits, a transmission gate, and a transmission-gate-substitute (TGS) circuit, and wherein: for each of the first and second NAND circuits, a first input is configured to receive corresponding first and second data signals, and a second input is configured to receive an enable signal; the first inverter is configured to receive an output of the first NAND circuit; the transmission gate and the TGS circuit are arranged as a combination circuit which is configured to receive an output of the second NAND circuit as a data input, and outputs of the first inverter and the second NAND circuit as control inputs; the second inverter is configured to receive an output of the combination circuit; and an output of the second inverter represents one of an enable XOR (EXOR) function or an enable XNR (EXNR) function.