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公开(公告)号：US12081215B2
公开(公告)日：2024-09-03
申请号：US18333284
申请日：2023-06-12
发明人： Yu-Lun Ou , Ji-Yung Lin , Yung-Chen Chien , Ruei-Wun Sun , Wei-Hsiang Ma , Jerry Chang Jui Kao , Shang-Chih Hsieh , Lee-Chung Lu
IPC分类号： H03K3/037 , H03K19/0185
CPC分类号： H03K19/018521 , H03K3/037
摘要： A circuit includes an input circuit, a level shifter circuit, an output circuit, and a first and a second feedback circuit. The input circuit is coupled to a first voltage supply, and configured to receive a first input signal, and to generate at least a second input signal. The level shifter circuit is coupled to a second voltage supply, and configured to generate at least a first and second signal responsive to at least the enable signal or the first input signal. The output circuit is coupled to at least the level shifter circuit and the second voltage supply, and configured to generate at least an output signal, a first and second feedback signal responsive to the first signal. The first and second feedback circuit are configured to receive the enable signal, and the inverted enable signal, and the corresponding first and second feedback signal.
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公开(公告)号：US20240037309A1
公开(公告)日：2024-02-01
申请号：US18345389
申请日：2023-06-30
发明人： Chi-Lin Liu , Shang-Chih Hsieh , Jian-Sing Li , Wei-Hsiang Ma , Yi-Hsun Chen , Cheok-Kei Lei
IPC分类号： G06F30/392 , G06F30/347 , G06F30/39 , H01L27/02
CPC分类号： G06F30/392 , G06F30/347 , G06F30/39 , H01L27/0207
摘要： A multiplexer circuit includes first and second fins each extending in an X-axis direction. First, second, third and fourth gates extend in a Y-axis direction perpendicular to the X-axis direction and contact the first and second fins. The first, second, third and fourth gates are configured to receive first, second, third and fourth data signals, respectively. Fifth, sixth, seventh and eighth gates extend in the Y-axis direction and contact the first and second fins, the fifth, sixth, seventh and eighth gates, and are configured to receive the first, second, third and fourth select signals, respectively. An input logic circuit is configured to provide an output at an intermediate node. A ninth gate extends in the Y-axis direction and contacts the first and second fins. An output logic circuit is configured to provide a selected one of the first, second, third and fourth data signals at an output terminal.
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公开(公告)号：US10664565B2
公开(公告)日：2020-05-26
申请号：US15936712
申请日：2018-03-27
发明人： Chi-Lin Liu , Sheng-Hsiung Chen , Jerry Chang-Jui Kao , Fong-Yuan Chang , Lee-Chung Lu , Shang-Chih Hsieh , Wei-Hsiang Ma
IPC分类号： G06F17/50
摘要： A method (of expanding a set of standard cells which comprise a library, the library being stored on a non-transitory computer-readable medium) includes: selecting one ad hoc group amongst ad hoc groups of elementary standard cells which are recurrent resulting in a selected group such that the elementary standard cells in the selected group having connections so as to represent a corresponding logic circuit, each elementary standard cell representing a logic gate, and the selected group corresponding providing a selected logical function which is representable correspondingly as a selected Boolean expression; generating, in correspondence to the selected group, one or more macro standard cells; and adding the one or more macro standard cells to, and thereby expanding, the set of standard cells; and wherein at least one aspect of the method is executed by a processor of a computer.
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公开(公告)号：US12074603B1
公开(公告)日：2024-08-27
申请号：US18313384
申请日：2023-05-08
IPC分类号： H03K3/037 , H03K3/3562
CPC分类号： H03K3/0372 , H03K3/0375 , H03K3/35625
摘要： The present disclosure provides a semiconductor device which includes a multiplexer, a master latch, and a slave latch. The multiplexer outputs an inverse of an input data signal or an inverse scan input signal according to a scan enable signal. The master latch is coupled to an output terminal of the multiplexer, and is configured to latch the inverse of the input data signal based on an input clock signal in response to the scan enable signal being in a low-logic state. The slave latch is coupled to the output terminal of the multiplexer through a first clocked CMOS inverter, and is configured to receive the input data signal and to output a latched slave latch data based on the input clock signal. A leakage-free dummy cell is disposed in a non-critical path of the master latch and the slave latch.
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公开(公告)号：US20240056061A1
公开(公告)日：2024-02-15
申请号：US18448027
申请日：2023-08-10
发明人： Chi-Lin Liu , Shang-Chih Hsieh , Wei-Hsiang Ma
摘要： A circuit includes a multi-bit flip flop, an integrated clock gating circuit connected to the multi-bit flip flop, and a control circuit connected to the integrated clock gating circuit and the multi-bit flip flop. The control circuit compares output data of the multi-bit flip flop corresponding to input data with the input data. The control circuit generates an enable signal based on comparing the output data of the multi-bit flip flop corresponding to the input data with the input data of the multi-bit flip flop. The control circuit provides the enable signal to the integrated clock gating circuit, wherein the integrated clock gating circuit provides, based on the enable signal, a clock signal to the multi-bit flip flop causing the multi-bit flip flop to toggle.
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公开(公告)号：US11757435B2
公开(公告)日：2023-09-12
申请号：US17815679
申请日：2022-07-28
发明人： Kai-Chi Huang , Yung-Chen Chien , Chi-Lin Liu , Wei-Hsiang Ma , Jerry Chang Jui Kao , Shang-Chih Hsieh , Lee-Chung Lu
IPC分类号： H03K3/037 , G06F1/3237 , H03K3/356 , H03K19/00
CPC分类号： H03K3/0375 , G06F1/3237 , H03K3/0372 , H03K3/356086 , H03K19/0016
摘要： A circuit includes first and second power nodes having differing first and second voltage levels, and a reference node having a reference voltage level. A master latch outputs a first data bit based on a received data bit; a slave latch includes a first inverter that outputs a second data bit based on the first data bit and a second inverter that outputs an output data bit based on a selected one of the first data bit or a third data bit; a level shifter outputs the third data bit based on a fourth data bit; and a retention latch outputs the fourth data bit based on the second data bit. The first and second inverters and the level shifter are coupled between the first power node and the reference node, and the retention latch includes a plurality of transistors coupled between the second power node and the reference node.
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公开(公告)号：US11694012B2
公开(公告)日：2023-07-04
申请号：US17853095
申请日：2022-06-29
发明人： Chi-Lin Liu , Shang-Chih Hsieh , Jian-Sing Li , Wei-Hsiang Ma , Yi-Hsun Chen , Cheok-Kei Lei
IPC分类号： G06F30/30 , H01L27/02 , G06F30/392 , G06F30/347 , G06F30/39
CPC分类号： G06F30/392 , G06F30/347 , G06F30/39 , H01L27/0207
摘要： A multiplexer circuit includes first and second fins each extending in an X-axis direction. First, second, third and fourth gates extend in a Y-axis direction perpendicular to the X-axis direction and contact the first and second fins. The first, second, third and fourth gates are configured to receive first, second, third and fourth data signals, respectively. Fifth, sixth, seventh and eighth gates extend in the Y-axis direction and contact the first and second fins, the fifth, sixth, seventh and eighth gates, and are configured to receive the first, second, third and fourth select signals, respectively. An input logic circuit is configured to provide an output at an intermediate node. A ninth gate extends in the Y-axis direction and contacts the first and second fins. An output logic circuit is configured to provide a selected one of the first, second, third and fourth data signals at an output terminal.
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公开(公告)号：US11677400B2
公开(公告)日：2023-06-13
申请号：US17835906
申请日：2022-06-08
发明人： Yu-Lun Ou , Ji-Yung Lin , Yung-Chen Chien , Ruei-Wun Sun , Wei-Hsiang Ma , Jerry Chang Jui Kao , Shang-Chih Hsieh , Lee-Chung Lu
IPC分类号： H03K3/037 , H03K19/0185
CPC分类号： H03K19/018521 , H03K3/037
摘要： A circuit includes an input circuit, a level shifter circuit, an output circuit, and a first and a second feedback circuit. The input circuit is coupled to a first voltage supply, and configured to receive a first input signal, and to generate at least a second input signal. The level shifter circuit is coupled to a second voltage supply, and configured to generate at least a first and second signal responsive to at least the enable signal or the first input signal. The output circuit is coupled to at least the level shifter circuit and the second voltage supply, and configured to generate at least an output signal, a first and second feedback signal responsive to the first signal. The first and second feedback circuit are configured to receive the enable signal, and the inverted enable signal, and the corresponding first and second feedback signal.
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公开(公告)号：US11526647B2
公开(公告)日：2022-12-13
申请号：US17115436
申请日：2020-12-08
发明人： Chi-Yu Lu , Ting-Wei Chiang , Hui-Zhong Zhuang , Jerry Chang Jui Kao , Pin-Dai Sue , Jiun-Jia Huang , Yu-Ti Su , Wei-Hsiang Ma
IPC分类号： G06F30/394 , G03F1/70 , G03F1/36 , G06F30/398
摘要： An integrated circuit includes a first type-one transistor, a second type-one transistor, a first type-two transistor, a second type-two transistor, a third type-one transistor, a fourth type-one transistor, and a fifth type-one transistor. The first type-one transistor has a gate configured to have a first supply voltage of a first power supply. The first type-two transistor has a gate configured to have a second supply voltage of the first power supply. The first active-region of the third type-one transistor is connected with an active-region of the first type-one transistor. The second active-region and the gate of the third type-one transistor are connected together. The first active-region of the fifth type-one transistor is connected with the gate of the third type-one transistor. The second active-region of the fifth type-one transistor is configured to have a first supply voltage of a second power supply.
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公开(公告)号：US20220327275A1
公开(公告)日：2022-10-13
申请号：US17853095
申请日：2022-06-29
发明人： Chi-Lin Liu , Shang-Chih Hsieh , Jian-Sing Li , Wei-Hsiang Ma , Yi-Hsun Chen , Cheok-Kei Lei
IPC分类号： G06F30/392 , G06F30/39 , H01L27/02
摘要： A multiplexer circuit includes first and second fins each extending in an X-axis direction. First, second, third and fourth gates extend in a Y-axis direction perpendicular to the X-axis direction and contact the first and second fins. The first, second, third and fourth gates are configured to receive first, second, third and fourth data signals, respectively. Fifth, sixth, seventh and eighth gates extend in the Y-axis direction and contact the first and second fins, the fifth, sixth, seventh and eighth gates, and are configured to receive the first, second, third and fourth select signals, respectively. An input logic circuit is configured to provide an output at an intermediate node. A ninth gate extends in the Y-axis direction and contacts the first and second fins. An output logic circuit is configured to provide a selected one of the first, second, third and fourth data signals at an output terminal.
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