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公开(公告)号：US09406791B2
公开(公告)日：2016-08-02
申请号：US14977112
申请日：2015-12-21
IPC分类号： H01L29/66 , H01L29/778 , H01L29/205 , H01L21/44 , H01L21/28 , H01L21/3205
CPC分类号： H01L29/7786 , H01L21/182 , H01L29/205 , H01L29/66545 , H01L29/7788 , H01L29/78681
摘要： Transistors, semiconductor devices and methods of manufacture thereof are disclosed. In one embodiment, a method of manufacturing a semiconductor device includes forming a transistor over a workpiece. The transistor includes a sacrificial gate material comprising a group III-V material. The method includes combining a metal (Me) with the group III-V material of the sacrificial gate material to form a gate of the transistor comprising a Me-III-V compound material.
摘要翻译： 公开了晶体管，半导体器件及其制造方法。 在一个实施例中，制造半导体器件的方法包括在工件上形成晶体管。 晶体管包括包含III-V族材料的牺牲栅极材料。 该方法包括将金属（Me）与牺牲栅极材料的III-V族材料组合以形成包含Me-III-V复合材料的晶体管的栅极。
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公开(公告)号：US09337109B2
公开(公告)日：2016-05-10
申请号：US13902326
申请日：2013-05-24
IPC分类号： H01L29/82 , H01L21/00 , H01L27/092 , H01L21/336 , H01L21/8234 , H01L21/8238 , H01L27/06 , H01L29/10
CPC分类号： H01L21/823821 , H01L21/823412 , H01L27/0605 , H01L27/0924 , H01L29/1054
摘要： A multi-threshold voltage (Vt) field-effect transistor (FET) formed through strain engineering is provided. An embodiment integrated circuit device includes a first transistor including a first channel region over a first buffer, the first channel region formed from a III-V semiconductor material and a second transistor including a second channel region over a second buffer, the second channel region formed from the III-V semiconductor material, the second buffer and the first buffer having a lattice mismatch. A first strain introduced by a lattice mismatch between the III-V semiconductor material and the first buffer is different than a second strain introduced by a lattice mismatch between the III-V semiconductor material and the second buffer. Therefore, the threshold voltage of the first transistor is different than the threshold voltage of the second transistor.
摘要翻译： 提供了通过应变工程形成的多阈值电压（Vt）场效应晶体管（FET）。 实施例集成电路装置包括：第一晶体管，包括第一缓冲器上的第一沟道区，由III-V半导体材料形成的第一沟道区和在第二缓冲区上包括第二沟道区的第二晶体管，形成第二沟道区 从III-V半导体材料，第二缓冲器和第一缓冲器具有晶格失配。 由III-V族半导体材料和第一缓冲层之间的晶格失配引入的第一应变与由III-V族半导体材料和第二缓冲层之间的晶格失配导入的第二应变不同。 因此，第一晶体管的阈值电压不同于第二晶体管的阈值电压。
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公开(公告)号：US20240357789A1
公开(公告)日：2024-10-24
申请号：US18362212
申请日：2023-07-31
发明人： Oreste Madia , Gerben Doornbos
IPC分类号： H10B10/00 , H01L23/528 , H01L29/423 , H01L29/66 , H01L29/775 , H01L29/786
CPC分类号： H10B10/125 , H01L23/5283 , H01L29/42392 , H01L29/66439 , H01L29/775 , H01L29/78642 , H01L29/7869 , H01L29/78696
摘要： A memory device includes a first n-type transistor and a second n-type transistor formed of a first channel extending along a vertical direction and wrapped by first, second, third, fourth, and fifth metal tracks; a third n-type transistor and a fourth n-type transistor formed of a second channel extending along the vertical direction and is wrapped by fourth, sixth, seventh, eighth, and ninth metal tracks; a first p-type transistor formed of a third channel extending along the vertical direction and is wrapped by second, third, and tenth metal tracks; and a second p-type transistor formed of a fourth channel extending along the vertical direction and is wrapped by sixth, seventh, and tenth metal tracks.
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公开(公告)号：US12027632B2
公开(公告)日：2024-07-02
申请号：US17233941
申请日：2021-04-19
IPC分类号： H01L29/786 , H01L29/66
CPC分类号： H01L29/78696 , H01L29/66742 , H01L29/78618 , H01L29/7869
摘要： A semiconductor structure includes a channel layer including an oxide semiconductor material, source/drain contacts disposed below the channel layer, and barrier regions that are in contact with the channel layer and that surround the source/drain contacts, respectively. Each of the barrier regions includes a material that receives hydrogen. A method for manufacturing the semiconductor structure is also provided.
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公开(公告)号：US11949020B2
公开(公告)日：2024-04-02
申请号：US18078113
申请日：2022-12-09
发明人： Marcus Johannes Henricus Van Dal , Blandine Duriez , Georgios Vellianitis , Gerben Doornbos , Mauricio Manfrini
CPC分类号： H01L29/7869 , H01L21/02565 , H01L21/02667 , H01L27/1207 , H01L27/1225 , H01L27/124 , H01L27/1255 , H01L29/24 , H01L29/66969 , H01L29/78648 , H01L29/78696 , H10B99/00
摘要： A transistor includes a first gate electrode, a first capping layer, a crystalline semiconductor oxide layer, a second capping layer, a first gate dielectric layer, and source/drain contacts. The first capping layer, the crystalline semiconductor oxide layer, and the second capping layer are sequentially disposed over the first gate electrode. Sidewalls of the second capping layer are aligned with sidewalls of the crystalline semiconductor oxide layer. The first gate dielectric layer is located between the first gate electrode and the first capping layer. The source/drain contacts are disposed on the second capping layer. The crystalline semiconductor oxide layer and the source/drain contacts are located on two opposite sides of the second capping layer.
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公开(公告)号：US20230389328A1
公开(公告)日：2023-11-30
申请号：US18358966
申请日：2023-07-26
发明人： Gerben Doornbos , Mauricio MANFRINI
CPC分类号： H10B51/30 , H01L29/6684 , H01L29/516 , H01L29/78391
摘要： A semiconductor includes a ferroelectric layer, a first semiconductor layer, a first gate, a second semiconductor layer, a second gate and contact structures. The ferroelectric layer has a first surface and a second surface opposite to the first surface. The first semiconductor layer is disposed on the first surface of the ferroelectric layer. The first gate is disposed on the first semiconductor layer over the first surface. The second semiconductor layer is disposed on the second surface of the ferroelectric layer. The second gate is disposed on the second semiconductor layer over the second surface. The contacts structures are connected to the first semiconductor layer and the second semiconductor layer.
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公开(公告)号：US20230361041A1
公开(公告)日：2023-11-09
申请号：US18347775
申请日：2023-07-06
IPC分类号： H01L27/088 , H01L23/535 , H01L23/48 , H01L27/12 , H01L21/74 , H01L29/417 , H01L29/66
CPC分类号： H01L23/535 , H01L21/743 , H01L23/481 , H01L27/088 , H01L27/1203 , H01L29/4175 , H01L29/66742 , H01L23/4825
摘要： The present disclosure relates to an integrated chip including a channel structure on a first substrate. A gate electrode overlies the channel structure. A first source/drain structure abuts the channel structure and is offset from the gate electrode. A conductive structure is disposed on the first substrate and underlies the first source/drain structure. A first contact extends from the first source/drain structure to the conductive structure.
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公开(公告)号：US20230047356A1
公开(公告)日：2023-02-16
申请号：US17401323
申请日：2021-08-13
IPC分类号： H01L29/267 , H01L29/51 , H01L21/28 , H01L29/66 , H01L29/78
摘要： A semiconductor device is provided. The semiconductor device includes a gate layer, a semiconductor layer and a ferroelectric layer disposed between the gate layer and the semiconductor layer. The semiconductor layer includes a first material containing a Group III element, a rare-earth element and a Group VI element, the ferroelectric layer includes a second material containing a Group III element, a rare-earth element and a Group V element and the gate layer includes a third material containing a Group III element and a rare-earth element. A method of fabricating a semiconductor device is also provided.
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公开(公告)号：US20230041622A1
公开(公告)日：2023-02-09
申请号：US17669378
申请日：2022-02-11
IPC分类号： H01L27/1159 , H01L29/66 , H01L29/78
摘要： A ferroelectric memory device includes a substrate, a gate electrode, a ferroelectric layer, and a pair of source/drain electrodes. The gate electrode is disposed over the substrate. The ferroelectric layer at least covers two adjacent side surfaces of the gate electrode. The pair of source/drain electrodes is over the substrate and disposed on two opposite sides of the gate electrode respectively.
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公开(公告)号：US09048122B2
公开(公告)日：2015-06-02
申请号：US14329587
申请日：2014-07-11
IPC分类号： H01L27/088 , H01L21/336 , H01L21/8234 , H01L27/11 , H01L29/66 , H01L29/78
CPC分类号： H01L27/1104 , H01L21/823418 , H01L21/823431 , H01L21/823437 , H01L27/088 , H01L27/0886 , H01L27/11 , H01L29/0847 , H01L29/6659 , H01L29/66681 , H01L29/66795 , H01L29/7817 , H01L29/7834 , H01L29/785
摘要： A device and method of fabricating the same are disclosed. In an example, a device includes a first fin Field Effect Transistors (finFET) formed on a substrate. The first finFET including a fin formed on the substrate. The device further includes a second finFET formed on the substrate. The first finFET and the second finFET share the fin and wherein the first finFET is without any low density doped (LDD) extension region in the substrate and wherein the second FinFET is associated with a first LDD extension region formed in the substrate such that a drive strength of the second finFET is greater relative to a drive strength of the first finFET.
摘要翻译： 公开了一种其制造方法及其制造方法。 在一个示例中，器件包括形成在衬底上的第一鳍场效应晶体管（finFET）。 第一finFET包括形成在基板上的翅片。 该器件还包括形成在衬底上的第二finFET。 第一finFET和第二finFET共享翅片，并且其中第一finFET在衬底中没有任何低密度掺杂（LDD）延伸区域，并且其中第二FinFET与在衬底中形成的第一LDD延伸区域相关联，使得驱动器 第二finFET的强度相对于第一finFET的驱动强度更大。
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