公开(公告)号：US12040270B2

公开(公告)日：2024-07-16

申请号：US18138528

申请日：2023-04-24

申请人： TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

发明人： Gerben Doornbos

IPC分类号： H01L23/528 ,  H01L21/768 ,  H01L21/8238 ,  H01L21/84 ,  H01L23/48 ,  H01L27/092 ,  H01L27/118 ,  H01L27/12

CPC分类号： H01L23/5286 ,  H01L21/76898 ,  H01L21/823821 ,  H01L21/823871 ,  H01L21/845 ,  H01L23/481 ,  H01L27/0924 ,  H01L27/11807 ,  H01L27/1211 ,  H01L2027/11881

摘要： A semiconductor device includes a substrate, a front side circuit disposed over a front surface of the substrate, and a backside power delivery circuit disposed over a back surface and including a back side power supply wiring coupled to a first potential. The front side circuit includes semiconductor fins and a first front side insulating layer covering bottom portions of the semiconductor fins, a plurality of buried power supply wirings embedded in the first front side insulating layer, the plurality of buried power supply wirings including a first buried power supply wiring and a second buried power supply wiring, and a power switch configured to electrically connect and disconnect the first buried power supply wiring and the second buried power supply wiring. The second buried power supply wiring is connected to the back side power supply wiring by a first through-silicon via passing through the substrate.

公开(公告)号：US12010856B2

公开(公告)日：2024-06-11

申请号：US17874284

申请日：2022-07-27

申请人： TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

发明人： Timothy Vasen ,  Mark Van Dal ,  Gerben Doornbos ,  Matthias Passlack

IPC分类号： H10K10/46 ,  H10K19/10 ,  H10K85/20

CPC分类号： H10K10/484 ,  H10K10/464 ,  H10K10/472 ,  H10K10/481 ,  H10K19/10 ,  H10K85/221

摘要： In a method of forming a gate-all-around field effect transistor (GAA FET), a bottom support layer is formed over a substrate and a first group of carbon nanotubes (CNTs) are disposed over the bottom support layer. A first support layer is formed over the first group of CNTs and the bottom support layer such that the first group of CNTs are embedded in the first support layer. A second group of carbon nanotubes (CNTs) are disposed over the first support layer. A second support layer is formed over the second group of CNTs and the first support layer such that the second group of CNTs are embedded in the second support layer. A fin structure is formed by patterning at least the first support layer and the second support layer.

公开(公告)号：US11955551B2

公开(公告)日：2024-04-09

申请号：US17855804

申请日：2022-07-01

申请人： TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

发明人： Georgios Vellianitis ,  Gerben Doornbos ,  Marcus Van Dal

IPC分类号： H01L29/78 ,  B82Y10/00 ,  H01L21/8238 ,  H01L21/84 ,  H01L29/16 ,  H01L29/417 ,  H01L29/423 ,  H01L29/66 ,  H01L29/775 ,  H01L29/786

CPC分类号： H01L29/785 ,  H01L21/845 ,  H01L29/1608 ,  H01L29/41791 ,  H01L29/42356 ,  H01L29/66795 ,  H01L2029/7858

摘要： A semiconductor device includes a gate-all-around field effect transistor (GAA FET). The GAA FET includes channel regions made of a first semiconductor material disposed over a bottom fin layer made of a second semiconductor material, and a source/drain region made of a third semiconductor material. The first semiconductor material is Si1-xGex, where 0.9≤x≤1.0, and the second semiconductor material is Si1-yGey, where y

公开(公告)号：US11791420B2

公开(公告)日：2023-10-17

申请号：US17233899

申请日：2021-04-19

申请人： TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

发明人： Marcus Johannes Henricus Van Dal ,  Gerben Doornbos ,  Georgios Vellianitis ,  Mauricio Manfrini

IPC分类号： H01L29/786 ,  H01L29/66

CPC分类号： H01L29/78696 ,  H01L29/66742 ,  H01L29/7869 ,  H01L29/78618

摘要： A semiconductor device includes a channel layer, source/drain contacts, and first barrier liners. The channel layer includes an oxide semiconductor material. The source/drain contacts are disposed in electrical contact with the channel layer. The first barrier liners surround the source/drain contacts, respectively, and include a hydrogen barrier material so as to prevent hydrogen from diffusion through the first barrier liners to the channel layer.

公开(公告)号：US11784219B2

公开(公告)日：2023-10-10

申请号：US17339171

申请日：2021-06-04

申请人： TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

发明人： Mark Van Dal ,  Gerben Doornbos ,  Chung-Te Lin

IPC分类号： H01L21/82 ,  H01L27/092 ,  H01L29/78 ,  H01L29/06 ,  H01L29/10 ,  H01L29/66 ,  H01L29/423 ,  H01L29/417 ,  H01L27/06 ,  H01L21/8238 ,  H01L21/822 ,  H01L29/40 ,  H01L29/08 ,  H01L29/786 ,  B82Y10/00 ,  H01L29/775 ,  H01L21/02

CPC分类号： H01L29/0673 ,  B82Y10/00 ,  H01L21/02236 ,  H01L21/8221 ,  H01L21/823807 ,  H01L21/823821 ,  H01L27/0688 ,  H01L27/0924 ,  H01L29/0653 ,  H01L29/0847 ,  H01L29/1037 ,  H01L29/401 ,  H01L29/41725 ,  H01L29/42376 ,  H01L29/42392 ,  H01L29/6681 ,  H01L29/66439 ,  H01L29/66545 ,  H01L29/66742 ,  H01L29/66772 ,  H01L29/775 ,  H01L29/785 ,  H01L29/78618 ,  H01L29/78654 ,  H01L29/78684 ,  H01L29/78696

摘要： Methods for forming semiconductor structures are provided. The method includes forming a fin structure over a substrate and forming a dummy gate structure across the fin structure. The method further includes forming a spacer layer on a sidewall of the fin structure at a source/drain region. The method further includes removing at least a portion of the spacer layer to enlarge the source/drain region and forming a source/drain structure in the source/drain region.

公开(公告)号：US11574927B2

公开(公告)日：2023-02-07

申请号：US17233162

申请日：2021-04-16

申请人： TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

发明人： Marcus Johannes Henricus Van Dal ,  Georgios Vellianitis ,  Gerben Doornbos

IPC分类号： H01L29/78 ,  H01L29/40 ,  H01L27/1159 ,  H01L21/28 ,  H01L29/24 ,  H01L29/51 ,  H01L29/16

摘要： A semiconductor device includes a gate electrode, a channel layer, and a ferroelectric layer. The ferroelectric layer includes a monocrystalline region located between the gate electrode and the channel layer to serve as a gate dielectric, and a polycrystalline region located at an edge of the gate electrode. A method for manufacturing the semiconductor device is also disclosed.

公开(公告)号：US20220384584A1

公开(公告)日：2022-12-01

申请号：US17878016

申请日：2022-07-31

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Georgios Vellianitis ,  Gerben Doornbos ,  Marcus Johannes Henricus Van Dal

IPC分类号： H01L29/22 ,  H01L29/78

摘要： A semiconductor device and a manufacturing method thereof are provided. The semiconductor device has a semiconductor layer and a gate structure located on the semiconductor layer. The semiconductor device has source and drain terminals disposed on the semiconductor layer, and a binary oxide layer located between the semiconductor layer and the source and drain terminals.

公开(公告)号：US09871104B2

公开(公告)日：2018-01-16

申请号：US14755083

申请日：2015-06-30

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Gerben Doornbos ,  Mark van Dal

IPC分类号： H01L21/265 ,  H01L29/66 ,  H01L29/04 ,  H01L29/08 ,  H01L29/78 ,  H01L29/06 ,  H01L21/324

CPC分类号： H01L29/0847 ,  H01L21/26506 ,  H01L21/26586 ,  H01L21/324 ,  H01L29/04 ,  H01L29/0673 ,  H01L29/0676 ,  H01L29/0688 ,  H01L29/167 ,  H01L29/42392 ,  H01L29/66439 ,  H01L29/66477 ,  H01L29/66666 ,  H01L29/775 ,  H01L29/78 ,  H01L29/7827

摘要： A nanowire comprises a source region, a drain region and a channel region. The source region is modified to reduce the lifetime of minority carriers within the source region. In an embodiment the modification may be performed by implanting either amorphizing dopants or lifetime reducing dopants. Alternatively, the source may be epitaxially grown with a different materials or process conditions to reduce the lifetime of minority carriers within the source region.

公开(公告)号：US20170365668A1

公开(公告)日：2017-12-21

申请号：US15676285

申请日：2017-08-14

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Gerben Doornbos ,  Krishna Kumar Bhuwalka ,  Matthias Passlack

IPC分类号： H01L29/205 ,  H01L29/10 ,  H01L29/66 ,  H01L29/78

CPC分类号： H01L29/205 ,  H01L29/1054 ,  H01L29/66795 ,  H01L29/785

摘要： A system and method for a channel region is disclosed. An embodiment comprises a channel region with multiple bi-layers comprising alternating complementary materials such as layers of InAs and layers of GaSb. The alternating layers of complementary materials provide desirable band gap characteristics for the channel region as a whole that individual layers of material may not.

公开(公告)号：US20160300911A1

公开(公告)日：2016-10-13

申请号：US15189913

申请日：2016-06-22

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Martin Christopher Holland ,  Georgios Vellianitis ,  Richard Kenneth Oxland ,  Krishna Kumar Bhuwalka ,  Gerben Doornbos

IPC分类号： H01L29/205 ,  H01L29/20 ,  H01L21/02 ,  H01L29/778 ,  H01L29/78 ,  H01L29/10 ,  H01L29/66

CPC分类号： H01L29/205 ,  H01L21/02538 ,  H01L29/1054 ,  H01L29/20 ,  H01L29/66545 ,  H01L29/66795 ,  H01L29/7787 ,  H01L29/785

摘要： Various heterostructures and methods of forming heterostructures are disclosed. A method includes removing portions of a substrate to form a temporary fin protruding above the substrate, forming a dielectric material over the substrate and over the temporary fin, removing the temporary fin to form a trench in the dielectric material, the trench exposing a portion of a first crystalline material of the substrate, forming a template material at least partially in the trench, the template material being a second crystalline material that is lattice mismatched to the first crystalline material, forming a barrier material over the template material, the barrier material being a third crystalline material, forming a device material over the barrier material, the device material being a fourth crystalline material, forming a gate stack over the device material, and forming a first source/drain region and a second source/drain region in the device material.

摘要翻译： 公开了形成异质结构的各种异质结构和方法。 一种方法包括去除衬底的部分以形成在衬底上突出的临时鳍片，在衬底上方并在临时鳍片之上形成介电材料，去除临时鳍片以在电介质材料中形成沟槽， 所述衬底的第一结晶材料至少部分地形成在所述沟槽中的模板材料，所述模板材料是与所述第一晶体材料晶格失配的第二结晶材料，在所述模板材料上形成阻挡材料，所述阻挡材料为 第三晶体材料，在所述阻挡材料上形成器件材料，所述器件材料是第四晶体材料，在所述器件材料上形成栅叠层，以及在所述器件中形成第一源极/漏极区域和第二源极/漏极区域 材料。