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公开(公告)号：US11955551B2
公开(公告)日：2024-04-09
申请号：US17855804
申请日：2022-07-01
IPC分类号： H01L29/78 , B82Y10/00 , H01L21/8238 , H01L21/84 , H01L29/16 , H01L29/417 , H01L29/423 , H01L29/66 , H01L29/775 , H01L29/786
CPC分类号： H01L29/785 , H01L21/845 , H01L29/1608 , H01L29/41791 , H01L29/42356 , H01L29/66795 , H01L2029/7858
摘要： A semiconductor device includes a gate-all-around field effect transistor (GAA FET). The GAA FET includes channel regions made of a first semiconductor material disposed over a bottom fin layer made of a second semiconductor material, and a source/drain region made of a third semiconductor material. The first semiconductor material is Si1-xGex, where 0.9≤x≤1.0, and the second semiconductor material is Si1-yGey, where y
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公开(公告)号：US11869949B2
公开(公告)日：2024-01-09
申请号：US17852393
申请日：2022-06-29
发明人： Georgios Vellianitis
IPC分类号： H01L29/417 , H01L29/40 , H01L29/423 , H01L29/78 , H01L29/08 , H01L29/10
CPC分类号： H01L29/41775 , H01L29/0865 , H01L29/1033 , H01L29/401 , H01L29/4232 , H01L29/4236 , H01L29/785 , H01L29/7813
摘要： A semiconductor device and a manufacturing method thereof are provided. The gate structure and the source and drain terminals are located in the insulating dielectric layer, and the source and drain terminals are located respectively at both opposite ends of the gate structure. The channel region is sandwiched between the gate structure and the source and drain terminals and surrounds the gate structure. The channel region extends between the source and drain terminals.
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公开(公告)号：US20230363291A1
公开(公告)日：2023-11-09
申请号：US18356168
申请日：2023-07-20
CPC分类号： H10N52/80 , H10B61/10 , H10N50/85 , H10N52/01 , H10N52/101
摘要： A semiconductor structure includes a storage element layer and a selector. The selector is electrically coupled to the storage element layer, and includes a first insulating layer, a second insulating layer, a third insulating layer, a first conductive layer and a second conductive layer. The first insulating layer, the second insulating layer and the third insulating layer are stacked up in sequence, wherein the second insulating layer is sandwiched in between the first insulating layer and the third insulating layer, and the first insulating layer and the third insulating layer include materials with higher band gap as compared with a material of the second insulating layer. The first conductive layer is connected to the first insulting layer, and the second conductive layer is connected to the third insulating layer.
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公开(公告)号：US11791420B2
公开(公告)日：2023-10-17
申请号：US17233899
申请日：2021-04-19
IPC分类号： H01L29/786 , H01L29/66
CPC分类号： H01L29/78696 , H01L29/66742 , H01L29/7869 , H01L29/78618
摘要： A semiconductor device includes a channel layer, source/drain contacts, and first barrier liners. The channel layer includes an oxide semiconductor material. The source/drain contacts are disposed in electrical contact with the channel layer. The first barrier liners surround the source/drain contacts, respectively, and include a hydrogen barrier material so as to prevent hydrogen from diffusion through the first barrier liners to the channel layer.
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公开(公告)号：US11574927B2
公开(公告)日：2023-02-07
申请号：US17233162
申请日：2021-04-16
摘要： A semiconductor device includes a gate electrode, a channel layer, and a ferroelectric layer. The ferroelectric layer includes a monocrystalline region located between the gate electrode and the channel layer to serve as a gate dielectric, and a polycrystalline region located at an edge of the gate electrode. A method for manufacturing the semiconductor device is also disclosed.
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公开(公告)号：US20220384584A1
公开(公告)日：2022-12-01
申请号：US17878016
申请日：2022-07-31
摘要： A semiconductor device and a manufacturing method thereof are provided. The semiconductor device has a semiconductor layer and a gate structure located on the semiconductor layer. The semiconductor device has source and drain terminals disposed on the semiconductor layer, and a binary oxide layer located between the semiconductor layer and the source and drain terminals.
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公开(公告)号：US20210391430A1
公开(公告)日：2021-12-16
申请号：US17111466
申请日：2020-12-03
发明人： Georgios Vellianitis
IPC分类号： H01L29/417 , H01L29/423 , H01L29/40
摘要： A semiconductor device and a manufacturing method thereof are provided. The gate structure and the source and drain terminals are located in the insulating dielectric layer, and the source and drain terminals are located respectively at both opposite ends of the gate structure. The channel region is sandwiched between the gate structure and the source and drain terminals and surrounds the gate structure. The channel region extends between the source and drain terminals.
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公开(公告)号：US09887084B2
公开(公告)日：2018-02-06
申请号：US15430845
申请日：2017-02-13
CPC分类号： H01L21/02647 , H01L21/02532 , H01L21/02538 , H01L21/02546 , H01L21/02549 , H01L21/02603 , H01L21/0262 , H01L21/02639 , H01L21/30604 , H01L29/0673 , H01L29/0676 , H01L29/66795
摘要： A method includes depositing an insulating layer over a substrate, the substrate including a first semiconductor material. The method also includes forming an opening in the insulating layer, the opening exposing a surface of the substrate. The method also includes growing a nanowire over the exposed surface of the substrate, the nanowire extending out of the opening away from the substrate, the nanowire including a second semiconductor material different from the first semiconductor material. The method also includes laterally growing the second semiconductor material on exposed sidewalls of the nanowire.
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公开(公告)号：US09741604B2
公开(公告)日：2017-08-22
申请号：US14977033
申请日：2015-12-21
IPC分类号： H01L29/78 , H01L21/762 , H01L21/306 , H01L29/06 , H01L29/10 , H01L29/66 , H01L21/764 , H01L29/165 , H01L29/205
CPC分类号： H01L21/76264 , H01L21/30604 , H01L21/764 , H01L29/0649 , H01L29/0653 , H01L29/1033 , H01L29/165 , H01L29/205 , H01L29/66477 , H01L29/66795 , H01L29/78 , H01L29/7853
摘要： A method includes performing an epitaxy to grow a semiconductor layer, which includes a top portion over a semiconductor region. The semiconductor region is between two insulation regions that are in a substrate. The method further includes recessing the insulation regions to expose portions of sidewalls of the semiconductor region, and etching a portion of the semiconductor region, wherein the etched portion of the semiconductor region is under and contacting a bottom surface of the semiconductor layer, wherein the semiconductor layer is spaced apart from an underlying region by an air gap. A gate dielectric and a gate electrode are formed over the semiconductor layer.
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公开(公告)号：US20170154772A1
公开(公告)日：2017-06-01
申请号：US15430845
申请日：2017-02-13
CPC分类号： H01L21/02647 , H01L21/02532 , H01L21/02538 , H01L21/02546 , H01L21/02549 , H01L21/02603 , H01L21/0262 , H01L21/02639 , H01L21/30604 , H01L29/0673 , H01L29/0676 , H01L29/66795
摘要： A method includes depositing an insulating layer over a substrate, the substrate including a first semiconductor material. The method also includes forming an opening in the insulating layer, the opening exposing a surface of the substrate. The method also includes growing a nanowire over the exposed surface of the substrate, the nanowire extending out of the opening away from the substrate, the nanowire including a second semiconductor material different from the first semiconductor material. The method also includes laterally growing the second semiconductor material on exposed sidewalls of the nanowire.
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