公开(公告)号：US20230386938A1

公开(公告)日：2023-11-30

申请号：US18447239

申请日：2023-08-09

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Huiching Chang ,  I-Ming Chang ,  Huang-Lin Chao

IPC分类号： H01L21/8238 ,  H01L29/66 ,  H01L29/78 ,  H01L29/06 ,  H01L29/423 ,  H01L29/49 ,  H01L29/51 ,  H01L29/786 ,  H01L21/02 ,  H01L21/28 ,  H01L27/092

CPC分类号： H01L21/823857 ,  H01L29/6684 ,  H01L29/78391 ,  H01L29/0665 ,  H01L29/42392 ,  H01L29/4908 ,  H01L29/516 ,  H01L29/7851 ,  H01L29/78696 ,  H01L21/0259 ,  H01L21/02192 ,  H01L21/0228 ,  H01L21/28088 ,  H01L21/823842 ,  H01L21/823807 ,  H01L21/823821 ,  H01L21/823871 ,  H01L29/66545 ,  H01L29/66795 ,  H01L29/66742 ,  H01L27/0924

摘要： A method of forming a semiconductor device includes forming a transistor comprising a gate stack on a semiconductor substrate by, at least, forming a first dielectric layer on the semiconductor substrate, forming a dipole layer on the dielectric layer; forming a second dielectric layer on the dipole layer, forming a conductive work function layer on the second dielectric layer, forming a gate electrode layer on the conductive work function layer. The method also includes varying a distance between dipole inducing elements in the dipole layer and a surface of the semiconductor substrate by tuning a thickness of the first dielectric layer to adjust a threshold voltage of the transistor.

公开(公告)号：US20140175513A1

公开(公告)日：2014-06-26

申请号：US13725330

申请日：2012-12-21

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Liang-Gi Yao ,  I-Ming Chang ,  Yasutoshi Okuno ,  Chih-Hao Chang ,  Shou Zen Chang ,  Clement Hsingien Wann

IPC分类号： H01L29/78 ,  H01L21/02

CPC分类号： H01L21/2807 ,  H01L21/02381 ,  H01L21/02532 ,  H01L29/1054 ,  H01L29/513 ,  H01L29/517 ,  H01L29/66545 ,  H01L29/66651 ,  H01L29/785

摘要： The present disclosure provides one embodiment of a semiconductor structure. The semiconductor structure includes a semiconductor substrate having a first semiconductor material and a first reactivity; and a low reactivity capping layer of disposed on the semiconductor substrate, wherein the low reactivity capping layer includes a second semiconductor material and a second reactivity less than the first reactivity, the low reactivity capping layer includes silicon germanium Si1−xGex and x is less than about 30%.

摘要翻译： 本公开提供了半导体结构的一个实施例。 半导体结构包括具有第一半导体材料和第一反应性的半导体衬底; 以及设置在所述半导体衬底上的低反应性覆盖层，其中所述低反应性覆盖层包括第二半导体材料和小于所述第一反应性的第二反应性，所述低反应性覆盖层包括硅锗Si1-xGex，并且x小于 约30％。

公开(公告)号：US20240150192A1

公开(公告)日：2024-05-09

申请号：US18411962

申请日：2024-01-12

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Hsiang-Pi CHANG ,  Chung-Liang Cheng ,  I-Ming Chang ,  Yao-Sheng Huang ,  Huang-Lin Chao

IPC分类号： C01F17/235

CPC分类号： C01F17/235 ,  B82Y40/00

摘要： A semiconductor device with different configurations of gate structures and a method of fabricating the same are disclosed. The method includes forming a fin structure on a substrate, forming a gate opening on the fin structure, forming a metallic oxide layer within the gate opening, forming a first dielectric layer on the metallic oxide layer, forming a second dielectric layer on the first dielectric layer, forming a work function metal (WFM) layer on the second dielectric layer, and forming a gate metal fill layer on the WFM layer. The forming the first dielectric layer includes depositing an oxide material with an oxygen areal density less than an oxygen areal density of the metallic oxide layer.

公开(公告)号：US20230395433A1

公开(公告)日：2023-12-07

申请号：US18214558

申请日：2023-06-27

申请人： TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

发明人： Yao-Sheng Huang ,  I-Ming Chang ,  Huang-Lin Chao

IPC分类号： H01L21/8238 ,  H01L29/66 ,  H01L29/06 ,  H01L29/161 ,  H01L29/24 ,  H01L29/423 ,  H01L29/417 ,  H01L29/786 ,  H01L21/02 ,  H01L27/092

CPC分类号： H01L21/823814 ,  H01L29/66742 ,  H01L29/0665 ,  H01L29/161 ,  H01L29/24 ,  H01L29/42392 ,  H01L29/41733 ,  H01L29/78618 ,  H01L29/78696 ,  H01L21/0259 ,  H01L21/02521 ,  H01L21/02532 ,  H01L21/02236 ,  H01L21/02252 ,  H01L21/823807 ,  H01L21/823864 ,  H01L21/823871 ,  H01L29/66545 ,  H01L29/66553 ,  H01L29/66636 ,  H01L27/092

摘要： Embodiments of the present disclosure provide a method of forming N-type and P-type source/drain features using one patterned mask and one self-aligned mask to increase windows of error tolerance and provide flexibilities for source/drain features of various shapes and/or volumes. In some embodiments, after forming a first type of source/drain features, a self-aligned mask layer is formed over the first type of source/drain features without using photolithography process, thus, avoid damaging the first type of source/drain features in the patterning process.

公开(公告)号：US11735483B2

公开(公告)日：2023-08-22

申请号：US17187283

申请日：2021-02-26

申请人： TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

发明人： Yao-Sheng Huang ,  I-Ming Chang ,  Huang-Lin Chao

IPC分类号： H01L21/8238 ,  H01L29/423 ,  H01L21/02 ,  H01L29/161 ,  H01L29/66 ,  H01L29/06 ,  H01L29/24 ,  H01L29/417 ,  H01L29/786 ,  H01L27/092

CPC分类号： H01L21/823814 ,  H01L21/0259 ,  H01L21/02236 ,  H01L21/02252 ,  H01L21/02521 ,  H01L21/02532 ,  H01L21/823807 ,  H01L21/823864 ,  H01L21/823871 ,  H01L27/092 ,  H01L29/0665 ,  H01L29/161 ,  H01L29/24 ,  H01L29/41733 ,  H01L29/42392 ,  H01L29/66545 ,  H01L29/66553 ,  H01L29/66636 ,  H01L29/66742 ,  H01L29/78618 ,  H01L29/78696

摘要： Embodiments of the present disclosure provide a method of forming N-type and P-type source/drain features using one patterned mask and one self-aligned mask to increase windows of error tolerance and provide flexibilities for source/drain features of various shapes and/or volumes. In some embodiments, after forming a first type of source/drain features, a self-aligned mask layer is formed over the first type of source/drain features without using photolithography process, thus, avoid damaging the first type of source/drain features in the patterning process.

公开(公告)号：US11626493B2

公开(公告)日：2023-04-11

申请号：US17345382

申请日：2021-06-11

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Hsueh-Wen Tsau ,  Chun-I Wu ,  Ziwei Fang ,  Huang-Lin Chao ,  I-Ming Chang ,  Chung-Liang Cheng ,  Chih-Cheng Lin

IPC分类号： H01L29/40 ,  H01L29/78 ,  H01L29/423 ,  H01L29/49 ,  H01L21/28 ,  H01L21/768 ,  H01L23/532 ,  H01L29/66 ,  H01L23/522 ,  H01L21/285 ,  H01L29/06

摘要： A semiconductor device structure is provided. The semiconductor device structure includes a substrate. The semiconductor device structure includes a gate stack over the substrate. The gate stack includes a gate dielectric layer, a first metal-containing layer, a silicon-containing layer, a second metal-containing layer, and a gate electrode layer sequentially stacked over the substrate. The silicon-containing layer is between the first metal-containing layer and the second metal-containing layer, and the silicon-containing layer is thinner than the second metal-containing layer.

公开(公告)号：US20220310846A1

公开(公告)日：2022-09-29

申请号：US17537339

申请日：2021-11-29

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Hsiang-Pi Chang ,  Yen-Tien Tung ,  Dawei Heh ,  Chung-Liang Cheng ,  I-Ming Chang ,  Yao-Sheng Huang ,  Tzer-Min Shen ,  Huang-Lin Chao

IPC分类号： H01L29/78 ,  H01L29/51 ,  H01L29/40 ,  H01L29/66

摘要： A semiconductor device includes a semiconductor substrate, an interfacial layer formed on the semiconductor substrate, a high-k dielectric layer formed on the interfacial layer, and a conductive gate electrode layer formed on the high-k dielectric layer. At least one of the high-k dielectric layer and the interfacial layer is doped with: a first dopant species, a second dopant species, and a third dopant species. The first dopant species and the second dopant species form a plurality of first dipole elements having a first polarity. The third dopant species forms a plurality of second dipole elements having a second polarity, and the first and second polarities are opposite.

公开(公告)号：US20220310457A1

公开(公告)日：2022-09-29

申请号：US17534377

申请日：2021-11-23

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Huiching Chang ,  I-Ming Chang ,  Huang-Lin Chao

IPC分类号： H01L21/8238 ,  H01L27/092 ,  H01L29/78 ,  H01L29/06 ,  H01L29/423 ,  H01L29/49 ,  H01L29/51 ,  H01L29/786 ,  H01L21/02 ,  H01L21/28 ,  H01L29/66

摘要： A method of forming a semiconductor device includes forming a transistor comprising a gate stack on a semiconductor substrate by, at least, forming a first dielectric layer on the semiconductor substrate, forming a dipole layer on the dielectric layer; forming a second dielectric layer on the dipole layer, forming a conductive work function layer on the second dielectric layer, forming a gate electrode layer on the conductive work function layer. The method also includes varying a distance between dipole inducing elements in the dipole layer and a surface of the semiconductor substrate by tuning a thickness of the first dielectric layer to adjust a threshold voltage of the transistor.

公开(公告)号：US11031291B2

公开(公告)日：2021-06-08

申请号：US16373235

申请日：2019-04-02

申请人： TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.

发明人： I-Ming Chang ,  Chung-Liang Cheng ,  Hsiang-Pi Chang ,  Hung-Chang Sun ,  Yao-Sheng Huang ,  Yu-Wei Lu ,  Fang-Wei Lee ,  Ziwei Fang ,  Huang-Lin Chao

IPC分类号： H01L21/8234 ,  H01L21/324 ,  H01L27/088 ,  H01L21/768 ,  H01L29/66 ,  H01L29/78 ,  H01L29/161 ,  H01L21/02 ,  H01L29/423 ,  H01L21/8238

摘要： A semiconductor structure includes a substrate including a first region and a second region, a first channel layer disposed in the first region and a second channel layer disposed in the second region, a first dielectric layer disposed on the first channel layer and a second dielectric layer disposed on the second channel layer, and a first gate electrode disposed on the first dielectric layer and a second gate electrode disposed on the second dielectric layer. The first channel layer in the first region includes Ge compound of a first Ge concentration, the second channel layer in the second region includes Ge compound of a second Ge concentration. The first Ge concentration in the first channel layer is greater than the second Ge concentration in the second channel layer.

公开(公告)号：US20160013308A1

公开(公告)日：2016-01-14

申请号：US14328350

申请日：2014-07-10

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Tung Ying Lee ,  Yu-Lien Huang ,  I-Ming Chang

IPC分类号： H01L29/78 ,  H01L29/51 ,  H01L29/36 ,  H01L29/66

CPC分类号： H01L29/785 ,  H01L29/66795

摘要： The present disclosure provides a semiconductor structure. In accordance with some embodiments, the semiconductor structure includes a substrate, one or more fins each including a first semiconductor layer formed over the substrate, an oxide layer formed wrapping over an upper portion of each of the one or more fins, and a gate stack including a high-K (HK) dielectric layer and a metal gate (MG) electrode formed wrapping over the oxide layer. The first semiconductor layer may include silicon germanium (SiGex), and the oxide layer may include silicon germanium oxide (SiGexOy).

摘要翻译： 本公开提供了一种半导体结构。 根据一些实施例，半导体结构包括衬底，每个包括形成在衬底上的第一半导体层的一个或多个鳍，形成在一个或多个翅片中的每一个的上部包裹的氧化物层，以及栅叠层 包括形成在氧化物层上的高K（HK）电介质层和金属栅极（MG）电极。 第一半导体层可以包括硅锗（SiGex），并且氧化物层可以包括硅锗氧化物（SiGexOy）。