公开(公告)号：US07808003B2

公开(公告)日：2010-10-05

申请号：US12285351

申请日：2008-10-02

申请人： Takeshi Endo ,  Eiichi Okuno

发明人： Takeshi Endo ,  Eiichi Okuno

IPC分类号： H01L29/15 ,  H01L31/0312

CPC分类号： H01L29/7802 ,  H01L29/0615 ,  H01L29/0619 ,  H01L29/0623 ,  H01L29/0692 ,  H01L29/0847 ,  H01L29/0878 ,  H01L29/1608 ,  H01L29/45 ,  H01L29/6606 ,  H01L29/66068 ,  H01L29/7395 ,  H01L29/7397 ,  H01L29/7813 ,  H01L29/7828 ,  H01L29/8083 ,  H01L29/861 ,  H01L29/872

摘要： A silicon carbide semiconductor device is disclosed. The silicon carbide semiconductor device includes a substrate; a drift layer having a first conductivity type and located on a first surface of the substrate; and a vertical type semiconductor element. The vertical type semiconductor element includes: an impurity layer having a second conductivity type, and located in a surface portion of the drift layer; and a first conductivity type region located in the drift layer, spaced away from the impurity layer, located closer to the substrate than the impurity layer, and having an impurity concentration higher than the drift layer.

摘要翻译： 公开了一种碳化硅半导体器件。 碳化硅半导体器件包括衬底; 具有第一导电类型且位于所述基板的第一表面上的漂移层; 和垂直型半导体元件。 垂直型半导体元件包括：具有第二导电类型的杂质层，并且位于漂移层的表面部分中; 以及位于漂移层中的离开杂质层的第一导电类型区域，位于比杂质层更靠近衬底的位置，并且具有高于漂移层的杂质浓度。

公开(公告)号：US20090267082A1

公开(公告)日：2009-10-29

申请号：US12385594

申请日：2009-04-14

申请人： Takeo Yamamoto ,  Takeshi Endo ,  Eiichi Okuno ,  Masaki Konishi ,  Hirokazu Fujiwara

发明人： Takeo Yamamoto ,  Takeshi Endo ,  Eiichi Okuno ,  Masaki Konishi ,  Hirokazu Fujiwara

IPC分类号： H01L29/872 ,  H01L29/24 ,  H01L21/329

CPC分类号： H01L29/861 ,  H01L21/0495 ,  H01L29/0657 ,  H01L29/1608 ,  H01L29/6606 ,  H01L29/7395 ,  H01L29/872

摘要： A semiconductor device includes: a semiconductor element having a first surface and a second surface; a first electrode disposed on the first surface of the element; a second electrode disposed on the second surface of the element; and an insulation film covers a part of the first electrode, the first surface of the element and a part of a sidewall of the element. The above semiconductor device has small dimensions and a high breakdown voltage.

摘要翻译： 半导体器件包括：具有第一表面和第二表面的半导体元件; 设置在所述元件的第一表面上的第一电极; 设置在所述元件的第二表面上的第二电极; 并且绝缘膜覆盖第一电极的一部分，元件的第一表面和元件的侧壁的一部分。 上述半导体器件具有小的尺寸和高的击穿电压。

公开(公告)号：US08168485B2

公开(公告)日：2012-05-01

申请号：US12461205

申请日：2009-08-04

申请人： Takeshi Endo ,  Eiichi Okuno ,  Takeo Yamamoto ,  Hirokazu Fujiwara ,  Masaki Konishi ,  Yukihiko Watanabe ,  Takashi Katsuno

发明人： Takeshi Endo ,  Eiichi Okuno ,  Takeo Yamamoto ,  Hirokazu Fujiwara ,  Masaki Konishi ,  Yukihiko Watanabe ,  Takashi Katsuno

IPC分类号： H01L29/812 ,  H01L21/338

CPC分类号： H01L29/872 ,  H01L29/456 ,  H01L29/47 ,  H01L29/66136 ,  H01L29/66143 ,  H01L29/861

摘要： A method of making a semiconductor device includes forming a p-type semiconductor region to an n-type semiconductor substrate in such a manner that the p-type semiconductor region is partially exposed to a top surface of the semiconductor substrate, forming a Schottky electrode of a first material in such a manner that the Schottky electrode is in Schottky contact with an n-type semiconductor region exposed to the top surface of the semiconductor substrate, and forming an ohmic electrode of a second material different from the first material in such a manner that the ohmic electrode is in ohmic contact with the exposed p-type semiconductor region. The Schottky electrode is formed earlier than the ohmic electrode.

摘要翻译： 制造半导体器件的方法包括：以p型半导体区域部分地暴露于半导体衬底的顶表面，形成p型半导体区域到n型半导体衬底，形成肖特基电极 以使肖特基电极与暴露于半导体衬底的顶表面的n型半导体区域肖特基接触的方式形成第一材料，并且以这种方式形成不同于第一材料的第二材料的欧姆电极 欧姆电极与暴露的p型半导体区域欧姆接触。 肖特基电极比欧姆电极早。

公开(公告)号：US20100032730A1

公开(公告)日：2010-02-11

申请号：US12461205

申请日：2009-08-04

申请人： Takeshi Endo ,  Eiichi Okuno ,  Takeo Yamamoto ,  Hirokazu Fujiwara ,  Masaki Konishi ,  Yukihiko Watanabe ,  Takashi Katsuno

发明人： Takeshi Endo ,  Eiichi Okuno ,  Takeo Yamamoto ,  Hirokazu Fujiwara ,  Masaki Konishi ,  Yukihiko Watanabe ,  Takashi Katsuno

IPC分类号： H01L29/812 ,  H01L21/338

CPC分类号： H01L29/872 ,  H01L29/456 ,  H01L29/47 ,  H01L29/66136 ,  H01L29/66143 ,  H01L29/861

摘要： A method of making a semiconductor device includes forming a p-type semiconductor region to an n-type semiconductor substrate in such a manner that the p-type semiconductor region is partially exposed to a top surface of the semiconductor substrate, forming a Schottky electrode of a first material in such a manner that the Schottky electrode is in Schottky contact with an n-type semiconductor region exposed to the top surface of the semiconductor substrate, and forming an ohmic electrode of a second material different from the first material in such a manner that the ohmic electrode is in ohmic contact with the exposed p-type semiconductor region. The Schottky electrode is formed earlier than the ohmic electrode.

摘要翻译： 制造半导体器件的方法包括：以p型半导体区域部分地暴露于半导体衬底的顶表面，形成p型半导体区域到n型半导体衬底，形成肖特基电极 以使肖特基电极与暴露于半导体衬底的顶表面的n型半导体区域肖特基接触的方式形成第一材料，并且以这种方式形成不同于第一材料的第二材料的欧姆电极 欧姆电极与暴露的p型半导体区域欧姆接触。 肖特基电极比欧姆电极早。

公开(公告)号：US20100006861A1

公开(公告)日：2010-01-14

申请号：US12458271

申请日：2009-07-07

申请人： Kensaku Yamamoto ,  Takeshi Endo ,  Eiichi Okuno

发明人： Kensaku Yamamoto ,  Takeshi Endo ,  Eiichi Okuno

IPC分类号： H01L29/12 ,  H01L29/78 ,  H01L21/04

CPC分类号： H01L29/7813 ,  H01L29/086 ,  H01L29/1608 ,  H01L29/4236 ,  H01L29/66068

摘要： A SiC semiconductor device includes: a substrate; a drift layer on a first side of the substrate; a trench in the drift layer; a base region contacting a sidewall of the trench; a source region in an upper portion of the base region; a gate electrode in the trench via a gate insulation film; a source electrode on the source region; and a drain electrode on a second side of the substrate. The source region has multi-layered structure including a first layer and a second layer. The first layer as an upper layer contacts the source electrode with ohmic contact. The second layer as a lower layer has an impurity concentration, which is lower than an impurity concentration of the first layer.

摘要翻译： SiC半导体器件包括：衬底; 在所述基板的第一侧上的漂移层; 漂移层中的沟槽; 接触所述沟槽的侧壁的基底区域; 在所述基区的上部的源极区; 通过栅极绝缘膜在沟槽中的栅电极; 源区上的源电极; 以及在所述基板的第二侧上的漏电极。 源区具有包括第一层和第二层的多层结构。 作为上层的第一层与欧姆接触的源电极接触。 作为下层的第二层的杂质浓度低于第一层的杂质浓度。

公开(公告)号：US20090090920A1

公开(公告)日：2009-04-09

申请号：US12285351

申请日：2008-10-02

申请人： Takeshi Endo ,  Eiichi Okuno

发明人： Takeshi Endo ,  Eiichi Okuno

IPC分类号： H01L29/24

CPC分类号： H01L29/7802 ,  H01L29/0615 ,  H01L29/0619 ,  H01L29/0623 ,  H01L29/0692 ,  H01L29/0847 ,  H01L29/0878 ,  H01L29/1608 ,  H01L29/45 ,  H01L29/6606 ,  H01L29/66068 ,  H01L29/7395 ,  H01L29/7397 ,  H01L29/7813 ,  H01L29/7828 ,  H01L29/8083 ,  H01L29/861 ,  H01L29/872

摘要： A silicon carbide semiconductor device is disclosed. The silicon carbide semiconductor device includes a substrate; a drift layer having a first conductivity type and located on a first surface of the substrate; and a vertical type semiconductor element. The vertical type semiconductor element includes: an impurity layer having a second conductivity type, and located in a surface portion of the drift layer; and a first conductivity type region located in the drift layer, spaced away from the impurity layer, located closer to the substrate than the impurity layer, and having an impurity concentration higher than the drift layer.

摘要翻译： 公开了一种碳化硅半导体器件。 碳化硅半导体器件包括衬底; 具有第一导电类型且位于所述基板的第一表面上的漂移层; 和垂直型半导体元件。 垂直型半导体元件包括：具有第二导电类型的杂质层，并且位于漂移层的表面部分中; 以及位于漂移层中的离开杂质层的第一导电类型区域，位于比杂质层更靠近衬底的位置，并且具有高于漂移层的杂质浓度。

公开(公告)号：US06452228B1

公开(公告)日：2002-09-17

申请号：US09626741

申请日：2000-07-26

申请人： Eiichi Okuno ,  Takeshi Endo ,  Kunihiko Hara

发明人： Eiichi Okuno ,  Takeshi Endo ,  Kunihiko Hara

IPC分类号： H01L2348

CPC分类号： H01L29/0696 ,  H01L21/049 ,  H01L29/045 ,  H01L29/1608 ,  H01L29/41766 ,  H01L29/4236 ,  H01L29/66068 ,  H01L29/7802 ,  H01L29/7813 ,  H01L29/7838 ,  H01L2924/0002 ,  H01L2924/00

摘要： A vertical type power MOSFET made of silicon carbide includes a surface channel layer doped with nitrogen as dopant with a concentration equal to or less than 1×1015 cm−3. Accordingly, when a gate oxide film is formed on the surface channel layer, an amount of silicon nitride produced in the gate oxide film and at the interface between the gate oxide film and the surface channel layer becomes extremely small. As a result, carrier traps are prevented from being produced by silicon nitride, resulting in stable FET characteristics and high reliability to the gate oxide film.

摘要翻译： 由碳化硅制成的垂直型功率MOSFET包括掺杂有氮作为掺杂剂的表面沟道层，其浓度等于或小于1×10 15 cm -3。 因此，当在表面沟道层上形成栅极氧化膜时，在栅极氧化膜中产生的氮化硅的量和栅氧化膜与表面沟道层之间的界面变得非常小。 结果，阻止了由氮化硅产生载流子阱，从而导致稳定的FET特性和对栅氧化膜的高可靠性。

公开(公告)号：US6165822A

公开(公告)日：2000-12-26

申请号：US224351

申请日：1999-01-04

申请人： Eiichi Okuno ,  Takeshi Endo ,  Shinji Amano

发明人： Eiichi Okuno ,  Takeshi Endo ,  Shinji Amano

IPC分类号： H01L29/16 ,  H01L21/04 ,  H01L29/04 ,  H01L29/06 ,  H01L29/12 ,  H01L29/24 ,  H01L29/423 ,  H01L29/78 ,  H01L21/335 ,  H01L21/338

CPC分类号： H01L29/0696 ,  H01L21/049 ,  H01L29/045 ,  H01L29/1608 ,  H01L29/41766 ,  H01L29/4236 ,  H01L29/66068 ,  H01L29/7802 ,  H01L29/7813 ,  H01L29/7838 ,  H01L2924/0002 ,  H01L2924/00

摘要： A vertical type power MOSFET made of silicon carbide includes a surface channel layer doped with nitrogen as dopant with a concentration equal to or less than 1.times.10.sup.15 cm.sup.-3. Accordingly, when a gate oxide film is formed on the surface channel layer, an amount of silicon nitride produced in the gate oxide film and at the interface between the gate oxide film and the surface channel layer becomes extremely small. As a result, carrier traps are prevented from being produced by silicon nitride, resulting in stable FET characteristics and high reliability to the gate oxide film.

摘要翻译： 由碳化硅制成的垂直型功率MOSFET包括掺杂有氮作为掺杂剂的表面沟道层，其浓度等于或小于1×10 15 cm -3。 因此，当在表面沟道层上形成栅极氧化膜时，在栅极氧化膜中产生的氮化硅的量和栅氧化膜与表面沟道层之间的界面变得非常小。 结果，阻止了由氮化硅产生载流子阱，从而导致稳定的FET特性和对栅氧化膜的高可靠性。

公开(公告)号：US08154074B2

公开(公告)日：2012-04-10

申请号：US12458271

申请日：2009-07-07

申请人： Kensaku Yamamoto ,  Takeshi Endo ,  Eiichi Okuno

发明人： Kensaku Yamamoto ,  Takeshi Endo ,  Eiichi Okuno

IPC分类号： H01L29/76 ,  H01L31/062

CPC分类号： H01L29/7813 ,  H01L29/086 ,  H01L29/1608 ,  H01L29/4236 ,  H01L29/66068

摘要： A SiC semiconductor device includes: a substrate; a drift layer on a first side of the substrate; a trench in the drift layer; a base region contacting a sidewall of the trench; a source region in an upper portion of the base region; a gate electrode in the trench via a gate insulation film; a source electrode on the source region; and a drain electrode on a second side of the substrate. The source region has multi-layered structure including a first layer and a second layer. The first layer as an upper layer contacts the source electrode with ohmic contact. The second layer as a lower layer has an impurity concentration, which is lower than an impurity concentration of the first layer.

摘要翻译： SiC半导体器件包括：衬底; 在所述基板的第一侧上的漂移层; 漂移层中的沟槽; 接触所述沟槽的侧壁的基底区域; 在所述基区的上部的源极区; 通过栅极绝缘膜在沟槽中的栅电极; 源区上的源电极; 以及在所述基板的第二侧上的漏电极。 源区具有包括第一层和第二层的多层结构。 作为上层的第一层与欧姆接触的源电极接触。 作为下层的第二层的杂质浓度低于第一层的杂质浓度。

公开(公告)号：US07968892B2

公开(公告)日：2011-06-28

申请号：US11882137

申请日：2007-07-31

申请人： Jun Kojima ,  Takeshi Endo ,  Eiichi Okuno ,  Yoshihito Mitsuoka ,  Yoshiyuki Hisada ,  Hideo Matsuki

发明人： Jun Kojima ,  Takeshi Endo ,  Eiichi Okuno ,  Yoshihito Mitsuoka ,  Yoshiyuki Hisada ,  Hideo Matsuki

IPC分类号： H01L31/0256

CPC分类号： H01L29/66068 ,  H01L21/02024 ,  H01L29/045 ,  H01L29/513 ,  H01L29/517 ,  H01L29/7828

摘要： A silicon carbide semiconductor device includes: a semiconductor substrate having a principal surface and a backside surface; a drift layer disposed on the principal surface; a base region disposed on the drift layer; a source region disposed on the base region; a surface channel layer disposed on both of the drift layer and the base region for connecting between the source region and the drift layer; a gate insulation film disposed on the surface channel layer and including a high dielectric constant film; a gate electrode disposed on the gate insulation film; a source electrode disposed on the source region; and a backside electrode disposed on the backside surface.

摘要翻译： 碳化硅半导体器件包括：具有主表面和背面的半导体衬底; 设置在主表面上的漂移层; 设置在漂移层上的基极区域; 设置在所述基底区域上的源极区域; 设置在所述漂移层和所述基极区域两者上的表面沟道层，用于在所述源极区域和所述漂移层之间连接; 栅极绝缘膜，设置在所述表面沟道层上并且包括高介电常数膜; 设置在所述栅极绝缘膜上的栅电极; 源电极，其设置在所述源极区域上; 以及设置在所述背面上的背面电极。