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    Semiconductor device making method
    1.
    发明授权
    Semiconductor device making method 有权
    半导体器件制造方法

    公开(公告)号：US08168485B2

    公开(公告)日：2012-05-01

    申请号：US12461205

    申请日：2009-08-04

    申请人： Takeshi Endo ,  Eiichi Okuno ,  Takeo Yamamoto ,  Hirokazu Fujiwara ,  Masaki Konishi ,  Yukihiko Watanabe ,  Takashi Katsuno

    发明人： Takeshi Endo ,  Eiichi Okuno ,  Takeo Yamamoto ,  Hirokazu Fujiwara ,  Masaki Konishi ,  Yukihiko Watanabe ,  Takashi Katsuno

    IPC分类号： H01L29/812 ,  H01L21/338

    CPC分类号： H01L29/872 ,  H01L29/456 ,  H01L29/47 ,  H01L29/66136 ,  H01L29/66143 ,  H01L29/861

    摘要： A method of making a semiconductor device includes forming a p-type semiconductor region to an n-type semiconductor substrate in such a manner that the p-type semiconductor region is partially exposed to a top surface of the semiconductor substrate, forming a Schottky electrode of a first material in such a manner that the Schottky electrode is in Schottky contact with an n-type semiconductor region exposed to the top surface of the semiconductor substrate, and forming an ohmic electrode of a second material different from the first material in such a manner that the ohmic electrode is in ohmic contact with the exposed p-type semiconductor region. The Schottky electrode is formed earlier than the ohmic electrode.

    摘要翻译： 制造半导体器件的方法包括：以p型半导体区域部分地暴露于半导体衬底的顶表面，形成p型半导体区域到n型半导体衬底，形成肖特基电极 以使肖特基电极与暴露于半导体衬底的顶表面的n型半导体区域肖特基接触的方式形成第一材料，并且以这种方式形成不同于第一材料的第二材料的欧姆电极 欧姆电极与暴露的p型半导体区域欧姆接触。 肖特基电极比欧姆电极早。

    Semiconductor device and method of making the same
    2.
    发明申请
    Semiconductor device and method of making the same 有权
    半导体器件及其制造方法

    公开(公告)号：US20100032730A1

    公开(公告)日：2010-02-11

    申请号：US12461205

    申请日：2009-08-04

    申请人： Takeshi Endo ,  Eiichi Okuno ,  Takeo Yamamoto ,  Hirokazu Fujiwara ,  Masaki Konishi ,  Yukihiko Watanabe ,  Takashi Katsuno

    发明人： Takeshi Endo ,  Eiichi Okuno ,  Takeo Yamamoto ,  Hirokazu Fujiwara ,  Masaki Konishi ,  Yukihiko Watanabe ,  Takashi Katsuno

    IPC分类号： H01L29/812 ,  H01L21/338

    CPC分类号： H01L29/872 ,  H01L29/456 ,  H01L29/47 ,  H01L29/66136 ,  H01L29/66143 ,  H01L29/861

    摘要： A method of making a semiconductor device includes forming a p-type semiconductor region to an n-type semiconductor substrate in such a manner that the p-type semiconductor region is partially exposed to a top surface of the semiconductor substrate, forming a Schottky electrode of a first material in such a manner that the Schottky electrode is in Schottky contact with an n-type semiconductor region exposed to the top surface of the semiconductor substrate, and forming an ohmic electrode of a second material different from the first material in such a manner that the ohmic electrode is in ohmic contact with the exposed p-type semiconductor region. The Schottky electrode is formed earlier than the ohmic electrode.

    摘要翻译： 制造半导体器件的方法包括：以p型半导体区域部分地暴露于半导体衬底的顶表面，形成p型半导体区域到n型半导体衬底，形成肖特基电极 以使肖特基电极与暴露于半导体衬底的顶表面的n型半导体区域肖特基接触的方式形成第一材料，并且以这种方式形成不同于第一材料的第二材料的欧姆电极 欧姆电极与暴露的p型半导体区域欧姆接触。 肖特基电极比欧姆电极早。

    Manufacturing method of a semiconductor device
    6.
    发明授权
    Manufacturing method of a semiconductor device 有权
    半导体器件的制造方法

    公开(公告)号：US07855131B2

    公开(公告)日：2010-12-21

    申请号：US12385782

    申请日：2009-04-20

    申请人： Hirokazu Fujiwara ,  Masaki Konishi ,  Takeo Yamamoto ,  Eiichi Okuno ,  Yukihiko Watanbe ,  Takashi Katsuno

    发明人： Hirokazu Fujiwara ,  Masaki Konishi ,  Takeo Yamamoto ,  Eiichi Okuno ,  Yukihiko Watanbe ,  Takashi Katsuno

    IPC分类号： H01L21/322

    CPC分类号： H01L29/47 ,  H01L21/046 ,  H01L29/1608 ,  H01L29/66143 ,  H01L29/872

    摘要： A manufacturing method of a semiconductor device comprises a process of doping conductive impurities in a silicon carbide substrate, a process of forming a cap layer on a surface of the silicon carbide substrate, a process of activating the conductive impurities doped in the silicon carbide substrate, a process of oxidizing the cap layer after a first annealing process, and a process of removing the oxidized cap layer. It is preferred that the cap layer is formed from material that includes metal carbide. Since the oxidation onset temperature of metal carbide is comparatively low, the oxidization of the cap layer becomes easy if metal carbide is included in the cap layer. Specifically, it is preferred that the cap layer is formed from metal carbide that has an oxidation onset temperature of 1000 degrees Celsius or below, such as tantalum carbide.

    摘要翻译： 半导体器件的制造方法包括在碳化硅衬底中掺杂导电杂质的工艺，在碳化硅衬底的表面上形成覆盖层的工艺，激活掺杂在碳化硅衬底中的导电杂质的工艺， 在第一退火工艺之后氧化盖层的工艺，以及去除氧化的盖层的工艺。 优选的是，盖层由包括金属碳化物的材料形成。 由于金属碳化物的氧化开始温度相对较低，如果在盖层中包括金属碳化物，则盖层的氧化变得容易。 具体而言，优选盖层由氧化开始温度为1000℃以下的金属碳化物形成，例如碳化钽。

    Manufacturing method of a semiconductor device
    7.
    发明申请
    Manufacturing method of a semiconductor device 有权
    半导体器件的制造方法

    公开(公告)号：US20090269908A1

    公开(公告)日：2009-10-29

    申请号：US12385782

    申请日：2009-04-20

    申请人： Hirokazu Fujiwara ,  Masaki Konishi ,  Takeo Yamamoto ,  Eiichi Okuno ,  Yukihiko Watanabe ,  Takashi Katsuno

    发明人： Hirokazu Fujiwara ,  Masaki Konishi ,  Takeo Yamamoto ,  Eiichi Okuno ,  Yukihiko Watanabe ,  Takashi Katsuno

    IPC分类号： H01L21/04

    CPC分类号： H01L29/47 ,  H01L21/046 ,  H01L29/1608 ,  H01L29/66143 ,  H01L29/872

    摘要： A manufacturing method of a semiconductor device comprises a process of doping conductive impurities in a silicon carbide substrate, a process of forming a cap layer on a surface of the silicon carbide substrate, a process of activating the conductive impurities doped in the silicon carbide substrate, a process of oxidizing the cap layer after a first annealing process, and a process of removing the oxidized cap layer. It is preferred that the cap layer is formed from material that includes metal carbide. Since the oxidation onset temperature of metal carbide is comparatively low, the oxidization of the cap layer becomes easy if metal carbide is included in the cap layer. Specifically, it is preferred that the cap layer is formed from metal carbide that has an oxidation onset temperature of 1000 degrees Celsius or below, such as tantalum carbide.

    摘要翻译： 半导体器件的制造方法包括在碳化硅衬底中掺杂导电杂质的工艺，在碳化硅衬底的表面上形成覆盖层的工艺，激活掺杂在碳化硅衬底中的导电杂质的工艺， 在第一退火工艺之后氧化盖层的工艺，以及去除氧化的盖层的工艺。 优选的是，盖层由包括金属碳化物的材料形成。 由于金属碳化物的氧化开始温度相对较低，如果在盖层中包括金属碳化物，则盖层的氧化变得容易。 具体而言，优选由碳化钽等氧化开始温度为1000℃以下的金属碳化物形成盖层。

    Semiconductor device manufacturing method
    8.
    发明授权
    Semiconductor device manufacturing method 有权
    半导体器件制造方法

    公开(公告)号：US08440524B2

    公开(公告)日：2013-05-14

    申请号：US13030790

    申请日：2011-02-18

    申请人： Hirokazu Fujiwara ,  Masaki Konishi ,  Jun Kawai ,  Takeo Yamamoto ,  Takeshi Endo ,  Takashi Katsuno ,  Yukihiko Watanabe ,  Narumasa Soejima

    发明人： Hirokazu Fujiwara ,  Masaki Konishi ,  Jun Kawai ,  Takeo Yamamoto ,  Takeshi Endo ,  Takashi Katsuno ,  Yukihiko Watanabe ,  Narumasa Soejima

    IPC分类号： H01L21/00

    CPC分类号： H01L29/7811 ,  C21D1/09 ,  C22F1/10 ,  H01L21/0485 ,  H01L21/0495 ,  H01L21/268 ,  H01L21/324 ,  H01L21/67115 ,  H01L29/0615 ,  H01L29/0619 ,  H01L29/1095 ,  H01L29/1608 ,  H01L29/45 ,  H01L29/47 ,  H01L29/6606 ,  H01L29/66068 ,  H01L29/7813 ,  H01L29/872

    摘要： A method for manufacturing a semiconductor device including a semiconductor substrate composed of silicon carbide, an upper surface electrode which contacts an upper surface of the substrate, and a lower surface electrode which contacts a lower surface of the substrate, the method including steps of: (a) forming an upper surface structure on the upper surface side of the substrate, and (b) forming a lower surface structure on the lower surface side of the substrate. The step (a) comprises steps of: (a1) depositing an upper surface electrode material layer on the upper surface of the substrate, the upper surface electrode material layer being a raw material layer of the upper surface electrode, and (a2) annealing the upper surface electrode material layer. The step (b) comprises steps of: (b1) depositing a lower surface electrode material layer on the lower surface of the substrate, the lower surface electrode material layer being a raw material layer of the lower surface electrode, and (b2) annealing the lower surface electrode material layer with a laser to make an ohmic contact between the lower surface electrode and the substrate.

    摘要翻译： 一种半导体器件的制造方法，该半导体器件包括由碳化硅构成的半导体衬底，与衬底的上表面接触的上表面电极和与衬底的下表面接触的下表面电极，该方法包括以下步骤：（ a）在基板的上表面侧上形成上表面结构，（b）在基板的下表面侧形成下表面结构。 步骤（a）包括以下步骤：（a1）在基板的上表面上沉积上表面电极材料层，上表面电极材料层是上表面电极的原料层，（a2）使 上表面电极材料层。 步骤（b）包括以下步骤：（b1）在基板的下表面上沉积下表面电极材料层，下表面电极材料层是下表面电极的原料层，（b2）使 下表面电极材料层用激光器在下表面电极和衬底之间形成欧姆接触。

    Diode
    9.
    发明申请
    Diode 审中-公开
    二极管

    公开(公告)号：US20090224353A1

    公开(公告)日：2009-09-10

    申请号：US12382012

    申请日：2009-03-05

    申请人： Takeo Yamamoto ,  Takeshi Endo ,  Yukihiko Watanabe ,  Takashi Katsuno ,  Masayasu Ishiko ,  Hirokazu Fujiwara ,  Masaki Konishi

    发明人： Takeo Yamamoto ,  Takeshi Endo ,  Yukihiko Watanabe ,  Takashi Katsuno ,  Masayasu Ishiko ,  Hirokazu Fujiwara ,  Masaki Konishi

    IPC分类号： H01L29/872

    CPC分类号： H01L29/872 ,  H01L27/0814 ,  H01L29/0649 ,  H01L29/417 ,  H01L29/861

    摘要： A diode includes the following: an n type semiconductor region; a p type semiconductor region provided in a part of a front face of the n type semiconductor region; an anode electrode (front face electrode) which adjoins a front face of the n type semiconductor region and a front face of the p type semiconductor region while at least forming a Schottky junction on a front face of the n type semiconductor region; and an insulating region which has a right-hand side (first side) and a left-hand side (second side) adjacent to the n type semiconductor region, the right-hand side facing a second n type semiconductor region which is located below the Schottky junction, the left-hand side facing a first n type semiconductor region which is located below a pn junction between the n type semiconductor region and the p type semiconductor region.

    摘要翻译： 二极管包括：n型半导体区域; 设置在n型半导体区域的正面的一部分中的p型半导体区域; 邻接n型半导体区域的前表面和p型半导体区域的正面的阳极电极（正面电极），同时至少在n型半导体区域的正面上形成肖特基结; 以及具有与n型半导体区域相邻的右侧（第一侧）和左侧（第二侧）的绝缘区域，所述右侧面向位于所述n型半导体区域下方的第二n型半导体区域 肖特基结，左手侧面对位于n型半导体区域和p型半导体区域之间的pn结的下方的第一n型半导体区域。