公开(公告)号：US06630389B2

公开(公告)日：2003-10-07

申请号：US10059030

申请日：2002-01-30

申请人： Takumi Shibata ,  Toshiyuki Morishita

发明人： Takumi Shibata ,  Toshiyuki Morishita

IPC分类号： H01L2176

CPC分类号： H01L21/3247 ,  H01L21/28167 ,  H01L21/324 ,  H01L29/4236 ,  H01L29/66348 ,  H01L29/7813

摘要： In a trench-gate type power MOSFET in which a gate electrode is formed on a gate oxide layer formed on a surface of a wall defining a trench, the trench is annealed by heating, for example, at the temperature between 1050° C. and 1150° C. in a hydrogen atmosphere before the gate oxide layer is formed. The crystal defects generated in a crystal adjacent to the trench are cured by the hydrogen annealing without enlarging the trench horizontal width, so that a trench having a high aspect ratio is provided while leak current at a PN junction is prevented. In addition, the breakdown voltage of the gate oxide layer is prevented from being lowered.

公开(公告)号：US06696323B2

公开(公告)日：2004-02-24

申请号：US10340746

申请日：2003-01-13

申请人： Hitoshi Yamaguchi ,  Toshio Sakakibara ,  Jun Sakakibara ,  Takumi Shibata ,  Toshiyuki Morishita

发明人： Hitoshi Yamaguchi ,  Toshio Sakakibara ,  Jun Sakakibara ,  Takumi Shibata ,  Toshiyuki Morishita

IPC分类号： H01L21332

CPC分类号： H01L29/7813 ,  H01L29/04 ,  H01L29/045 ,  H01L29/0696 ,  H01L29/41741 ,  H01L29/41766 ,  H01L29/4236 ,  H01L29/4238 ,  H01L29/66348 ,  H01L29/66378 ,  H01L29/66659 ,  H01L29/66704 ,  H01L29/66734 ,  H01L29/66787 ,  H01L29/7393 ,  H01L29/7397 ,  H01L29/749 ,  H01L29/78 ,  H01L29/7803 ,  H01L29/7809 ,  H01L29/7816 ,  H01L29/7817 ,  H01L29/7824 ,  H01L29/7825 ,  H01L29/7828 ,  H01L29/7835

摘要： In a semiconductor device, a p-type base region is provided in an n−-type substrate to extend from a principal surface of the substrate in a perpendicular direction to the principal surface. An n+-type source region extends in the p-type base region from the principal surface in the perpendicular direction, and an n+-type drain region extends in the substrate separately from the p-type base region with a drift region interposed therebetween. A trench is formed to penetrate the p-type base region from the n+-type source region in a direction parallel to the principal surface. A gate electrode is formed in the trench through a gate insulating film. Accordingly, a channel region can be formed with a channel width in a depth direction of the trench when a voltage is applied to the gate electrode.

摘要翻译： 在半导体器件中，p型基极区域设置在n型衬底中，从衬底的主表面沿垂直于主表面的方向延伸。 n +型源极区域在垂直方向上从主表面在p型基极区域中延伸，并且n +型漏极区域在p型基极区域中与p型基极区域分开延伸， 漂移区域。 形成沟槽，以在平行于主表面的方向上从n +型源极区域穿透p型基极区域。 栅电极通过栅极绝缘膜形成在沟槽中。 因此，当向栅电极施加电压时，可以在沟槽的深度方向上形成沟道区域。

公开(公告)号：US08604565B2

公开(公告)日：2013-12-10

申请号：US13083732

申请日：2011-04-11

申请人： Tetsuo Fujii ,  Minekazu Sakai ,  Takumi Shibata

发明人： Tetsuo Fujii ,  Minekazu Sakai ,  Takumi Shibata

IPC分类号： H01L29/82

CPC分类号： G01L9/0005

摘要： A physical quantity detection device includes: an insulating layer; a semiconductor layer on the insulating layer; and first and second electrodes in the semiconductor layer. Each electrode has a wall part, one of which includes two diaphragms and a cover part. The diaphragms facing each other provide a hollow cylinder having an opening covered by the cover part. One diaphragm faces the other wall part or one diaphragm in the other wall part. A distance between the one diaphragm and the other wall part or the one diaphragm in the other wall part is changed with pressure difference between reference pressure in the hollow cylinder and pressure of an outside when a physical quantity is applied to the diaphragms. The physical quantity is detected by a capacitance between the first and second electrodes.

摘要翻译： 物理量检测装置包括：绝缘层; 绝缘层上的半导体层; 以及半导体层中的第一和第二电极。 每个电极具有壁部分，其中一个包括两个隔膜和盖部分。 彼此相对的隔膜提供具有由盖部分覆盖的开口的中空圆柱体。 一个隔膜面对另一个壁部分或另一个壁部分的一个隔膜。 当物理量施加到隔膜时，一个隔膜和另一个壁部分中的另一个壁部分或一个隔膜之间的距离随空心圆柱体中的参考压力和外部压力之间的压力差而改变。 物理量由第一和第二电极之间的电容检测。

公开(公告)号：US20130012004A1

公开(公告)日：2013-01-10

申请号：US13541885

申请日：2012-07-05

申请人： Hiroshi OHTSUKI ,  Takumi Shibata

发明人： Hiroshi OHTSUKI ,  Takumi Shibata

IPC分类号： H01L21/306

CPC分类号： H01L21/3065 ,  H01L21/30604 ,  H01L29/0634 ,  H01L29/1095 ,  H01L29/66734 ,  H01L29/7813

摘要： A manufacturing method of a semiconductor substrate includes: forming a trench in a semiconductor board by a dry etching method; etching a surface portion of an inner wall of the trench by a chemical etching method so that a first damage layer is removed, wherein the surface portion has a thickness equal to or larger than 50 nanometers; and performing a heat treatment at temperature equal to or higher than 1050° C. in non-oxidizing and non-azotizing gas so that crystallinity of a second damage layer is recovered, wherein the second damage layer is disposed under the first damage layer. The crystallinity around the trench is sufficiently recovered

摘要翻译： 半导体衬底的制造方法包括：通过干蚀刻法在半导体板中形成沟槽; 通过化学蚀刻方法蚀刻沟槽的内壁的表面部分，从而去除第一损伤层，其中表面部分具有等于或大于50纳米的厚度; 并且在非氧化和非氮化气体中在等于或高于1050℃的温度下进行热处理，从而回收第二损伤层的结晶度，其中第二损伤层设置在第一损伤层下面。 沟槽周围的结晶度充分回收

公开(公告)号：US08349693B2

公开(公告)日：2013-01-08

申请号：US13024347

申请日：2011-02-10

申请人： Takumi Shibata ,  Shouichi Yamauchi

发明人： Takumi Shibata ,  Shouichi Yamauchi

IPC分类号： H01L21/336

CPC分类号： H01L29/7813 ,  H01L29/045 ,  H01L29/0634 ,  H01L29/66734

摘要： A semiconductor device includes a silicon substrate having a (110)-oriented surface, a PN column layer disposed on the (110)-oriented surface, a channel-forming layer disposed on the PN column layer, a plurality of source regions disposed at a surface portion of the channel-forming layer, and gate electrodes penetrate through the channel-forming layer. The PN column layer includes first columns having a first conductivity type and second columns having a second conductivity type which are alternately arranged in such a manner that the first columns contact the second columns on (111)-oriented surfaces, respectively. The gate electrodes are adjacent to the source regions, respectively, and each of the gate electrodes has side surfaces that cross the contact surfaces of the first columns and the second columns in a plane of the silicon substrate.

摘要翻译： 半导体器件包括具有（110）取向表面的硅衬底，设置在（110）取向表面上的PN列层，设置在PN列层上的沟道形成层，设置在 沟道形成层的表面部分和栅电极穿过沟道形成层。 PN列层包括具有第一导电类型的第一列和具有第二导电类型的第二列，这些第一列以这样的方式交替布置，使得第一列分别在（111）取向的表面上接触第二列。 栅电极分别与源区相邻，并且每个栅电极具有在硅衬底的平面中与第一列和第二列的接触表面交叉的侧表面。

公开(公告)号：US07905303B2

公开(公告)日：2011-03-15

申请号：US12685360

申请日：2010-01-11

申请人： Kenji Takenaka ,  Takumi Shibata

发明人： Kenji Takenaka ,  Takumi Shibata

IPC分类号： B62D51/06

CPC分类号： B25J9/0009

摘要： Disclosed is a legged locomotion robot which is structurally simple and is provided with a tiptoe portion in a foot at a low cost. The legged locomotion robot includes an upper body; two locomotive legs connected to the upper body through a joint; and a locomotive foot connected to a tip end of the leg through a joint; wherein the foot is provided with a foot sole serving as a ground contacting portion of the foot, a curved portion is formed at a predefined distance from a tip end of the foot sole, crossing the foot sole laterally, and the curved portion is configured to be thinner than a tiptoe portion of the foot sole.

摘要翻译： 公开了一种腿式运动机器人，其结构简单，并且以低成本在脚中设置有脚尖部分。 腿式运动机器人包括上身; 两条机车通过接头与上身相连; 以及通过接头连接到所述腿的末端的机车脚; 其特征在于，所述脚部设置有用作所述足部的接地部的足底部，弯曲部形成在与所述脚底的前端隔开预定距离的位置，所述弯曲部与所述脚底横向交叉， 比脚底的脚尖部分更薄。

公开(公告)号：US07104501B2

公开(公告)日：2006-09-12

申请号：US10619623

申请日：2003-07-16

申请人： Daiya Yamashita ,  Fumihiko Shikano ,  Hiroshi Kato ,  Akira Kaneko ,  Takumi Shibata

发明人： Daiya Yamashita ,  Fumihiko Shikano ,  Hiroshi Kato ,  Akira Kaneko ,  Takumi Shibata

IPC分类号： B64C3/20

CPC分类号： B23H9/00 ,  B23H7/02 ,  B23H9/10 ,  B64C27/473

摘要： It is an object to provide a blade member for an airplane which is simple in structure, and moreover is excellent with respects to weight, aerodynamic performance, cost, strength and durability. A vane of a double-slotted flap includes: an outer skin area surrounded by a first outer skin, a second outer skin, a leading edge and a trailing edge each having a predetermined wall thickness. Front and rear reinforcing areas are provided that extend in a span direction within the outer skin area and are connected to the first outer skin and the second outer skin. The outer skin area and the reinforcing areas are integrally formed by wire electrical discharge-machining. The first outer skin and the second outer skin respectively have thickened portions thicker than the other portions, and the trailing edge is formed to have a thickness which is approximately zero. This blade member can be simplified in structure, leading to reductions in the number of parts, number of assembling steps and weight. Moreover, no step nor seam is generated on a surface of the blade member, and hence it is possible to prevent an increase in drag and the generation of corrosion.

摘要翻译： 本发明的目的是提供一种结构简单的用于飞机的叶片构件，并且在重量，空气动力学性能，成本，强度和耐久性方面都是优异的。 双开口翼片的叶片包括：由第一外皮，第二外皮，前缘和后缘围绕的外皮区域，每个具有预定的壁厚。 提供前后加强区域，其在外皮肤区域内沿跨度方向延伸并连接到第一外皮和第二外皮。 外皮区域和加强区域通过电线放电加工一体形成。 第一外皮和第二外皮分别具有比其他部分更厚的加厚部分，并且后缘形成为具有近似为零的厚度。 该叶片构件可以简化结构，从而减少零件数量，组装步骤数量和重量。 此外，在叶片构件的表面上不产生台阶或接缝，因此可以防止阻力的增加和腐蚀的产生。

公开(公告)号：US06812097B2

公开(公告)日：2004-11-02

申请号：US10361782

申请日：2003-02-10

申请人： Takumi Shibata

发明人： Takumi Shibata

IPC分类号： H01L218247

CPC分类号： H01L27/11568 ,  H01L27/115 ,  Y10S438/954

摘要： A method is provided for manufacturing a MONOS type non-volatile memory device. The method comprises the following steps: a step of pattering a stopper layer and a first conductive layer; a step of forming an ONO film composed of a first silicon oxide layer, a silicon nitride layer and a second silicon oxide layer above a semiconductor substrate and on both sides of the first conductive layer; a step of forming a second conductive layer above the ONO film 220; a step of anisotropically etching the second conductive layer, and then isotropically etching the same, thereby forming control gates in the form of sidewalls through the ONO films on both side surfaces of the first conductive layer; and a step of patterning the first conductive layer to form a word gate.

摘要翻译： 提供了一种用于制造MONOS型非易失性存储器件的方法。 该方法包括以下步骤：形成止挡层和第一导电层的步骤; 在第一导电层的两面上形成由第一氧化硅层，氮化硅层和第二氧化硅层构成的ONO膜的工序; 在ONO膜220上形成第二导电层的步骤; 各向异性蚀刻第二导电层，然后各向同性地蚀刻第二导电层，从而通过第一导电层的两个侧表面上的ONO膜形成侧壁形式的控制栅; 以及图案化第一导电层以形成字门的步骤。

公开(公告)号：US6051212A

公开(公告)日：2000-04-18

申请号：US147393

申请日：1998-12-16

申请人： Hisao Kado ,  Takumi Shibata ,  Fujio Kobayashi ,  Masaki Kubota

发明人： Hisao Kado ,  Takumi Shibata ,  Fujio Kobayashi ,  Masaki Kubota

IPC分类号： A23L1/28 ,  A23L1/30 ,  A61K8/99 ,  A61Q19/00 ,  A61K7/00 ,  A23F1/00

CPC分类号： A61K8/99 ,  A23L31/00 ,  A23L33/145 ,  A61Q19/00 ,  Y10S514/844 ,  Y10S514/846

摘要： In accordance with the present invention, it is provided a method for producing a yeast extract with the improvement in the color and odor characteristic to yeast extract and with no modification of the useful substances such as amino acid, etc. compared with conventional yeast extract.By a simple method in accordance with the present invention, color and characteristic odor can be removed, with almost no loss of the contents of useful substances such as amino acid, etc. from the yeast extract solution produced in a conventional manner. Because the resulting yeast extract can be mixed with other materials for use, the yeast extract is applicable to various fields, for example for cosmetic products and healthy foods other than seasonings, which expectantly enlarges the applicable range of the yeast extract.

摘要翻译： PCT No.PCT / JP98 / 01741 Sec。 371日期1998年12月16日第 102（e）日期1998年12月16日PCT提交1998年4月16日PCT公布。 公开号WO98 / 46089 日期1998年10月22日根据本发明，提供了酵母提取物的颜色和气味特征的改善和氨基酸等有用物质的改性等的生产酵母提取物的方法。 与常规酵母提取物。 通过根据本发明的简单方法，可以除去以常规方式制备的酵母提取物溶液中的颜色和特征气味几乎不损失诸如氨基酸等有用物质的含量。 因为所得到的酵母提取物可以与其他材料混合使用，所以酵母提取物适用于各种领域，例如除了调味料之外的化妆品和健康食品，预期扩大酵母提取物的适用范围。

公开(公告)号：US20120032312A1

公开(公告)日：2012-02-09

申请号：US13258268

申请日：2010-03-25

申请人： Syouji Nogami ,  Hitoshi Goto ,  Takumi Shibata ,  Tsuyoshi Yamamoto

发明人： Syouji Nogami ,  Hitoshi Goto ,  Takumi Shibata ,  Tsuyoshi Yamamoto

IPC分类号： H01L29/02 ,  H01L21/20

CPC分类号： H01L29/7813 ,  H01L21/02381 ,  H01L21/02494 ,  H01L21/02532 ,  H01L21/02576 ,  H01L21/02579 ,  H01L21/0262 ,  H01L29/0634 ,  H01L29/1095 ,  H01L29/66734

摘要： A semiconductor substrate which allows desired electrical characteristics to be more easily acquired, a semiconductor device of the same, and a method of producing the semiconductor substrate. The method of producing this semiconductor substrate is provided with: a first epitaxial layer forming step (S1) of forming a first epitaxial layer; a trench forming step (S2) of forming trenches in the first epitaxial layer; and epitaxial layer forming steps (S3, S4, S5) of forming epitaxial layers on the first epitaxial layer and inside the trenches, using a plurality of growth conditions including differing growth rates, so as to fill the trenches, and keeping the concentration of dopant taken into the epitaxial layers constant in the plurality of growth conditions.

摘要翻译： 允许更容易获得所需电特性的半导体衬底及其半导体器件，以及制造半导体衬底的方法。 制造该半导体基板的方法具有：形成第一外延层的第一外延层形成工序（S1） 在第一外延层中形成沟槽的沟槽形成步骤（S2）; 以及外延层形成步骤（S3，S4，S5），其使用包括不同生长速率的多个生长条件在第一外延层和沟槽内部形成外延层，以便填充沟槽，并保持掺杂剂的浓度 在多个生长条件下被吸收到外延层中。