公开(公告)号：US06525375B1

公开(公告)日：2003-02-25

申请号：US09688154

申请日：2000-10-16

申请人： Hitoshi Yamaguchi ,  Toshio Sakakibara ,  Jun Sakakibara ,  Takumi Shibata ,  Toshiyuki Morishita

发明人： Hitoshi Yamaguchi ,  Toshio Sakakibara ,  Jun Sakakibara ,  Takumi Shibata ,  Toshiyuki Morishita

IPC分类号： H01L2976

CPC分类号： H01L29/7813 ,  H01L29/04 ,  H01L29/045 ,  H01L29/0696 ,  H01L29/41741 ,  H01L29/41766 ,  H01L29/4236 ,  H01L29/4238 ,  H01L29/66348 ,  H01L29/66378 ,  H01L29/66659 ,  H01L29/66704 ,  H01L29/66734 ,  H01L29/66787 ,  H01L29/7393 ,  H01L29/7397 ,  H01L29/749 ,  H01L29/78 ,  H01L29/7803 ,  H01L29/7809 ,  H01L29/7816 ,  H01L29/7817 ,  H01L29/7824 ,  H01L29/7825 ,  H01L29/7828 ,  H01L29/7835

摘要： In a semiconductor device, a p-type base region is provided in an n−-type substrate to extend from a principal surface of the substrate in a perpendicular direction to the principal surface. An n+-type source region extends in the p-type base region from the principal surface in the perpendicular direction, and an n+-type drain region extends in the substrate separately from the p-type base region with a drift region interposed therebetween. A trench is formed to penetrate the p-type base region from the n+-type source region in a direction parallel to the principal surface. A gate electrode is formed in the trench through a gate insulating film. Accordingly, a channel region can be formed with a channel width in a depth direction of the trench when a voltage is applied to the gate electrode.

摘要翻译： 在半导体器件中，p型基极区域设置在n型衬底中，以从垂直于主表面的方向从衬底的主表面延伸。 n +型源极区域在垂直方向上从主表面延伸到p型基极区域中，并且n +型漏极区域在p型基极区域中与P型基极区域分开延伸，并且其间插入漂移区域。 形成沟槽，以在平行于主表面的方向上从n +型源极区域穿透p型基极区域。 栅电极通过栅极绝缘膜形成在沟槽中。 因此，当向栅电极施加电压时，可以在沟槽的深度方向上形成沟道区域。

公开(公告)号：US06630389B2

公开(公告)日：2003-10-07

申请号：US10059030

申请日：2002-01-30

申请人： Takumi Shibata ,  Toshiyuki Morishita

发明人： Takumi Shibata ,  Toshiyuki Morishita

IPC分类号： H01L2176

CPC分类号： H01L21/3247 ,  H01L21/28167 ,  H01L21/324 ,  H01L29/4236 ,  H01L29/66348 ,  H01L29/7813

摘要： In a trench-gate type power MOSFET in which a gate electrode is formed on a gate oxide layer formed on a surface of a wall defining a trench, the trench is annealed by heating, for example, at the temperature between 1050° C. and 1150° C. in a hydrogen atmosphere before the gate oxide layer is formed. The crystal defects generated in a crystal adjacent to the trench are cured by the hydrogen annealing without enlarging the trench horizontal width, so that a trench having a high aspect ratio is provided while leak current at a PN junction is prevented. In addition, the breakdown voltage of the gate oxide layer is prevented from being lowered.

公开(公告)号：US06696323B2

公开(公告)日：2004-02-24

申请号：US10340746

申请日：2003-01-13

申请人： Hitoshi Yamaguchi ,  Toshio Sakakibara ,  Jun Sakakibara ,  Takumi Shibata ,  Toshiyuki Morishita

发明人： Hitoshi Yamaguchi ,  Toshio Sakakibara ,  Jun Sakakibara ,  Takumi Shibata ,  Toshiyuki Morishita

IPC分类号： H01L21332

CPC分类号： H01L29/7813 ,  H01L29/04 ,  H01L29/045 ,  H01L29/0696 ,  H01L29/41741 ,  H01L29/41766 ,  H01L29/4236 ,  H01L29/4238 ,  H01L29/66348 ,  H01L29/66378 ,  H01L29/66659 ,  H01L29/66704 ,  H01L29/66734 ,  H01L29/66787 ,  H01L29/7393 ,  H01L29/7397 ,  H01L29/749 ,  H01L29/78 ,  H01L29/7803 ,  H01L29/7809 ,  H01L29/7816 ,  H01L29/7817 ,  H01L29/7824 ,  H01L29/7825 ,  H01L29/7828 ,  H01L29/7835

摘要： In a semiconductor device, a p-type base region is provided in an n−-type substrate to extend from a principal surface of the substrate in a perpendicular direction to the principal surface. An n+-type source region extends in the p-type base region from the principal surface in the perpendicular direction, and an n+-type drain region extends in the substrate separately from the p-type base region with a drift region interposed therebetween. A trench is formed to penetrate the p-type base region from the n+-type source region in a direction parallel to the principal surface. A gate electrode is formed in the trench through a gate insulating film. Accordingly, a channel region can be formed with a channel width in a depth direction of the trench when a voltage is applied to the gate electrode.

摘要翻译： 在半导体器件中，p型基极区域设置在n型衬底中，从衬底的主表面沿垂直于主表面的方向延伸。 n +型源极区域在垂直方向上从主表面在p型基极区域中延伸，并且n +型漏极区域在p型基极区域中与p型基极区域分开延伸， 漂移区域。 形成沟槽，以在平行于主表面的方向上从n +型源极区域穿透p型基极区域。 栅电极通过栅极绝缘膜形成在沟槽中。 因此，当向栅电极施加电压时，可以在沟槽的深度方向上形成沟道区域。

公开(公告)号：US06495883B2

公开(公告)日：2002-12-17

申请号：US10060379

申请日：2002-02-01

申请人： Takumi Shibata ,  Shoichi Yamauchi ,  Yasushi Urakami ,  Toshiyuki Morishita

发明人： Takumi Shibata ,  Shoichi Yamauchi ,  Yasushi Urakami ,  Toshiyuki Morishita

IPC分类号： H01L2976

CPC分类号： H01L29/7813 ,  H01L29/045 ,  H01L29/4232 ,  H01L29/42368 ,  H01L29/4238

摘要： A semiconductor device has a dielectric strength for a gate oxide film at a trench bottom that is higher than that of side walls used for channels. An n+0 type substrate 1 having substrate plane orientation of (110) is prepared, and the side walls of a trench where channels are formed are in (100) planes. The other, non-channel forming, side walls of the trench are in (110) planes. Thus, the growth rate of the gate oxide film 7 in the non-channel forming side walls and the trench bottom is faster than that in the channel forming side walls. As a result, the film thickness at the non-channel-forming side walls and the trench bottom is greater than that of the channel-forming side walls. Accordingly, the device has high mobility, and there is no drop of dielectric strength due to partial reduction of the thickness of the gate oxide film 7. This achieves both a reduction of the ON resistance and an increase in the dielectric strength of the semiconductor device.

摘要翻译： 半导体器件在沟槽底部具有比用于沟道的侧壁高的栅极氧化膜的介电强度。 制备具有（110）基板平面取向的n + 0型基板1，并且形成通道的沟槽的侧壁在（100）平面中。 沟槽的另一个非通道形成侧壁在（110）平面中。 因此，非通道形成侧壁和沟槽底部中的栅极氧化膜7的生长速度比形成沟道的侧壁的生长速度快。 结果，在非沟道形成侧壁和沟槽底部处的膜厚度大于沟道形成侧壁的膜厚度。 因此，器件具有高迁移率，并且由于栅极氧化膜7的厚度的部分减小而不会降低介电强度。这实现了导通电阻的降低和半导体器件的介电强度的增加 。

公开(公告)号：US07364980B2

公开(公告)日：2008-04-29

申请号：US11539441

申请日：2006-10-06

申请人： Syouji Nogami ,  Tomonori Yamaoka ,  Shoichi Yamauchi ,  Hitoshi Yamaguchi ,  Takumi Shibata

发明人： Syouji Nogami ,  Tomonori Yamaoka ,  Shoichi Yamauchi ,  Hitoshi Yamaguchi ,  Takumi Shibata

IPC分类号： H01L21/76

CPC分类号： C30B25/165 ,  H01L21/02381 ,  H01L21/0243 ,  H01L21/02532 ,  H01L21/0262 ,  H01L21/02636 ,  H01L29/0634

摘要： Closure at the opening of a trench with an epitaxial film is restrained, and thereby, filling morphology in the trenches is improved. A method for manufacturing a semiconductor substrate includes a step for growing an epitaxial layer 11 on the surface of a silicon substrate 13, a step of forming a trench 14 in this epitaxial layer, and a step of filling the inside of the trench 14 with the epitaxial film 12, wherein mixed gas made by mixing halogenoid gas into silicon source gas is circulated as material gas in filling the inside of the trench with the epitaxial film, and when the standard flow rate of the halogenoid gas is defined as Xslm and the film formation speed of the epitaxial film formed by the circulation of the silicon source gas is defined as Yμm/min, in the case when the aspect ratio of the trench is less than 10, an expression Y

摘要翻译： 在具有外延膜的沟槽的开口处的闭合被抑制，从而提高了沟槽中的填充形态。 一种制造半导体衬底的方法包括在硅衬底13的表面上生长外延层11的步骤，在该外延层中形成沟槽14的步骤，以及将沟槽14内部填充的步骤 外延膜12，其中通过将卤素气体混入硅源气体而制成的混合气体作为原料气体循环，用外延膜填充沟槽内部，当将卤化物气体的标准流量定义为Xslm时，膜 通过硅源气体的循环形成的外延膜的形成速度定义为Ymum / min，在沟槽的纵横比小于10的情况下，满足表达式Y <0.2X + 0.10，在 沟槽的纵横比在10以上且小于20的情况下，满足表达式Y <0.2X + 0.05，在沟槽的纵横比为20以上的情况下，表达式Y <0.2× 满意

公开(公告)号：US20070082455A1

公开(公告)日：2007-04-12

申请号：US11539441

申请日：2006-10-06

申请人： Syouji NOGAMI ,  Tomonori Yamaoka ,  Shoichi Yamauchi ,  Hitoshi Yamaguchi ,  Takumi Shibata

发明人： Syouji NOGAMI ,  Tomonori Yamaoka ,  Shoichi Yamauchi ,  Hitoshi Yamaguchi ,  Takumi Shibata

IPC分类号： H01L21/76

CPC分类号： C30B25/165 ,  H01L21/02381 ,  H01L21/0243 ,  H01L21/02532 ,  H01L21/0262 ,  H01L21/02636 ,  H01L29/0634

摘要： Closure at the opening of a trench with an epitaxial film is restrained, and thereby, filling morphology in the trenches is improved. A method for manufacturing a semiconductor substrate includes a step for growing an epitaxial layer 11 on the surface of a silicon substrate 13, a step of forming a trench 14 in this epitaxial layer, and a step of filling the inside of the trench 14 with the epitaxial film 12, wherein mixed gas made by mixing halogenoid gas into silicon source gas is circulated as material gas in filling the inside of the trench with the epitaxial film, and when the standard flow rate of the halogenoid gas is defined as Xslm and the film formation speed of the epitaxial film formed by the circulation of the silicon source gas is defined as Yμm/min, in the case when the aspect ratio of the trench is less than 10, an expression Y

摘要翻译： 在具有外延膜的沟槽的开口处的闭合被抑制，从而提高了沟槽中的填充形态。 一种制造半导体衬底的方法包括在硅衬底13的表面上生长外延层11的步骤，在该外延层中形成沟槽14的步骤，以及将沟槽14内部填充的步骤 外延膜12，其中通过将卤素气体混入硅源气体而制成的混合气体作为原料气体循环，用外延膜填充沟槽内部，当将卤化物气体的标准流量定义为Xslm时，膜 通过硅源气体的循环形成的外延膜的形成速度定义为Ymum / min，在沟槽的纵横比小于10的情况下，满足表达式Y <0.2X + 0.10，在 沟槽的纵横比在10以上且小于20的情况下，满足表达式Y <0.2X + 0.05，在沟槽的纵横比为20以上的情况下，表达式Y <0.2× 满意

公开(公告)号：US08604565B2

公开(公告)日：2013-12-10

申请号：US13083732

申请日：2011-04-11

申请人： Tetsuo Fujii ,  Minekazu Sakai ,  Takumi Shibata

发明人： Tetsuo Fujii ,  Minekazu Sakai ,  Takumi Shibata

IPC分类号： H01L29/82

CPC分类号： G01L9/0005

摘要： A physical quantity detection device includes: an insulating layer; a semiconductor layer on the insulating layer; and first and second electrodes in the semiconductor layer. Each electrode has a wall part, one of which includes two diaphragms and a cover part. The diaphragms facing each other provide a hollow cylinder having an opening covered by the cover part. One diaphragm faces the other wall part or one diaphragm in the other wall part. A distance between the one diaphragm and the other wall part or the one diaphragm in the other wall part is changed with pressure difference between reference pressure in the hollow cylinder and pressure of an outside when a physical quantity is applied to the diaphragms. The physical quantity is detected by a capacitance between the first and second electrodes.

摘要翻译： 物理量检测装置包括：绝缘层; 绝缘层上的半导体层; 以及半导体层中的第一和第二电极。 每个电极具有壁部分，其中一个包括两个隔膜和盖部分。 彼此相对的隔膜提供具有由盖部分覆盖的开口的中空圆柱体。 一个隔膜面对另一个壁部分或另一个壁部分的一个隔膜。 当物理量施加到隔膜时，一个隔膜和另一个壁部分中的另一个壁部分或一个隔膜之间的距离随空心圆柱体中的参考压力和外部压力之间的压力差而改变。 物理量由第一和第二电极之间的电容检测。

公开(公告)号：US20130012004A1

公开(公告)日：2013-01-10

申请号：US13541885

申请日：2012-07-05

申请人： Hiroshi OHTSUKI ,  Takumi Shibata

发明人： Hiroshi OHTSUKI ,  Takumi Shibata

IPC分类号： H01L21/306

CPC分类号： H01L21/3065 ,  H01L21/30604 ,  H01L29/0634 ,  H01L29/1095 ,  H01L29/66734 ,  H01L29/7813

摘要： A manufacturing method of a semiconductor substrate includes: forming a trench in a semiconductor board by a dry etching method; etching a surface portion of an inner wall of the trench by a chemical etching method so that a first damage layer is removed, wherein the surface portion has a thickness equal to or larger than 50 nanometers; and performing a heat treatment at temperature equal to or higher than 1050° C. in non-oxidizing and non-azotizing gas so that crystallinity of a second damage layer is recovered, wherein the second damage layer is disposed under the first damage layer. The crystallinity around the trench is sufficiently recovered

摘要翻译： 半导体衬底的制造方法包括：通过干蚀刻法在半导体板中形成沟槽; 通过化学蚀刻方法蚀刻沟槽的内壁的表面部分，从而去除第一损伤层，其中表面部分具有等于或大于50纳米的厚度; 并且在非氧化和非氮化气体中在等于或高于1050℃的温度下进行热处理，从而回收第二损伤层的结晶度，其中第二损伤层设置在第一损伤层下面。 沟槽周围的结晶度充分回收

公开(公告)号：US08349693B2

公开(公告)日：2013-01-08

申请号：US13024347

申请日：2011-02-10

申请人： Takumi Shibata ,  Shouichi Yamauchi

发明人： Takumi Shibata ,  Shouichi Yamauchi

IPC分类号： H01L21/336

CPC分类号： H01L29/7813 ,  H01L29/045 ,  H01L29/0634 ,  H01L29/66734

摘要： A semiconductor device includes a silicon substrate having a (110)-oriented surface, a PN column layer disposed on the (110)-oriented surface, a channel-forming layer disposed on the PN column layer, a plurality of source regions disposed at a surface portion of the channel-forming layer, and gate electrodes penetrate through the channel-forming layer. The PN column layer includes first columns having a first conductivity type and second columns having a second conductivity type which are alternately arranged in such a manner that the first columns contact the second columns on (111)-oriented surfaces, respectively. The gate electrodes are adjacent to the source regions, respectively, and each of the gate electrodes has side surfaces that cross the contact surfaces of the first columns and the second columns in a plane of the silicon substrate.

摘要翻译： 半导体器件包括具有（110）取向表面的硅衬底，设置在（110）取向表面上的PN列层，设置在PN列层上的沟道形成层，设置在 沟道形成层的表面部分和栅电极穿过沟道形成层。 PN列层包括具有第一导电类型的第一列和具有第二导电类型的第二列，这些第一列以这样的方式交替布置，使得第一列分别在（111）取向的表面上接触第二列。 栅电极分别与源区相邻，并且每个栅电极具有在硅衬底的平面中与第一列和第二列的接触表面交叉的侧表面。

公开(公告)号：US07905303B2

公开(公告)日：2011-03-15

申请号：US12685360

申请日：2010-01-11

申请人： Kenji Takenaka ,  Takumi Shibata

发明人： Kenji Takenaka ,  Takumi Shibata

IPC分类号： B62D51/06

CPC分类号： B25J9/0009

摘要： Disclosed is a legged locomotion robot which is structurally simple and is provided with a tiptoe portion in a foot at a low cost. The legged locomotion robot includes an upper body; two locomotive legs connected to the upper body through a joint; and a locomotive foot connected to a tip end of the leg through a joint; wherein the foot is provided with a foot sole serving as a ground contacting portion of the foot, a curved portion is formed at a predefined distance from a tip end of the foot sole, crossing the foot sole laterally, and the curved portion is configured to be thinner than a tiptoe portion of the foot sole.

摘要翻译： 公开了一种腿式运动机器人，其结构简单，并且以低成本在脚中设置有脚尖部分。 腿式运动机器人包括上身; 两条机车通过接头与上身相连; 以及通过接头连接到所述腿的末端的机车脚; 其特征在于，所述脚部设置有用作所述足部的接地部的足底部，弯曲部形成在与所述脚底的前端隔开预定距离的位置，所述弯曲部与所述脚底横向交叉， 比脚底的脚尖部分更薄。