公开(公告)号：US5751022A

公开(公告)日：1998-05-12

申请号：US806153

申请日：1997-02-25

申请人： Norio Yasuhara ,  Akio Nakagawa ,  Tomoko Matsudai ,  Hideyuki Funaki

发明人： Norio Yasuhara ,  Akio Nakagawa ,  Tomoko Matsudai ,  Hideyuki Funaki

IPC分类号： H01L29/74 ,  H01L29/745 ,  H01L29/749 ,  H01L31/111

CPC分类号： H01L29/749 ,  H01L29/7412 ,  H01L29/7436 ,  H01L29/7455

摘要： A semiconductor device is disclosed having a thyristor region coupled to a semiconductor switching device and a semiconductor rectifier. During turn-off operation, holes are drained from the p-type base region of the thyristor region through the semiconductor rectifier and to the cathode of the thyristor. During turn-on, electrons are supplied to an n-type emitter region of the thyristor from the cathode electrode through the semiconductor switching device.

摘要翻译： 公开了具有耦合到半导体开关器件和半导体整流器的晶闸管区域的半导体器件。 在关断操作期间，从晶闸管区域的p型基极区域通过半导体整流器和晶闸管的阴极排出孔。 在导通期间，电子通过半导体开关器件从阴极电极提供给晶闸管的n型发射极区域。

公开(公告)号：US5241210A

公开(公告)日：1993-08-31

申请号：US642565

申请日：1991-01-18

申请人： Akio Nakagawa ,  Norio Yasuhara

发明人： Akio Nakagawa ,  Norio Yasuhara

IPC分类号： H01L21/336 ,  H01L21/74 ,  H01L21/762 ,  H01L27/06 ,  H01L27/092 ,  H01L27/12 ,  H01L29/06 ,  H01L29/40 ,  H01L29/739 ,  H01L29/74 ,  H01L29/745 ,  H01L29/749 ,  H01L29/78 ,  H01L29/786 ,  H01L29/861

CPC分类号： H01L29/7824 ,  H01L21/74 ,  H01L21/76264 ,  H01L21/76297 ,  H01L27/0623 ,  H01L27/0922 ,  H01L27/1203 ,  H01L29/404 ,  H01L29/405 ,  H01L29/407 ,  H01L29/408 ,  H01L29/66772 ,  H01L29/7394 ,  H01L29/7436 ,  H01L29/7455 ,  H01L29/749 ,  H01L29/7835 ,  H01L29/78624 ,  H01L29/8611 ,  H01L21/76275 ,  H01L21/76286 ,  H01L29/402

摘要： A high breakdown voltage semiconductor device includes a semiconductor substrate, a first insulating film formed on the semiconductor substrate, a first semiconductor region formed on the first insulating film, a second semiconductor region of a first conductivity type having an impurity concentration higher than that of the first semiconductor region and selectively formed on a surface portion of the first semiconductor region, a third semiconductor region having an impurity concentration lower than that of the second semiconductor region and formed on the surface portion of the first semiconductor region so as to be adjacent to or near the second semiconductor region and a fourth semiconductor region of a second conductivity type having an impurity concentration higher than that of the first semiconductor region and formed on the surface portion of the first semiconductor region so as to be outside the third semiconductor region. A fifth semiconductor region having an impurity concentration lower than that of the second or fourth semiconductor region is formed on a bottom portion of the first semiconductor region. When a reverse bias is applied between the second and fourth semiconductor regions, a depletion layer extends vertically in the first semiconductor region and laterally in the fifth semiconductor region. The applied voltage is divided in both the directions and a high breakdown voltage can be obtained.

摘要翻译： 高击穿电压半导体器件包括半导体衬底，形成在半导体衬底上的第一绝缘膜，形成在第一绝缘膜上的第一半导体区域，具有高于第一绝缘膜的杂质浓度的第一导电类型的第二半导体区域 第一半导体区域，并且选择性地形成在第一半导体区域的表面部分上，第三半导体区域具有杂质浓度低于第二半导体区域的杂质浓度，并形成在第一半导体区域的表面部分上，以便邻近或 在第二半导体区域附近形成杂质浓度高于第一半导体区域的第二导电类型的第四半导体区域，并且形成在第一半导体区域的表面部分上，以便在第三半导体区域的外部。 在第一半导体区域的底部形成有杂质浓度低于第二或第四半导体区域的第五半导体区域。 当在第二和第四半导体区域之间施加反向偏压时，耗尽层在第一半导体区域中垂直延伸并且在第五半导体区域中横向延伸。 施加的电压在两个方向上被分割，并且可以获得高的击穿电压。

公开(公告)号：US08981473B2

公开(公告)日：2015-03-17

申请号：US13410739

申请日：2012-03-02

申请人： Ryo Wada ,  Kaori Yoshioka ,  Norio Yasuhara ,  Tomoko Matsudai ,  Yuichi Goto

发明人： Ryo Wada ,  Kaori Yoshioka ,  Norio Yasuhara ,  Tomoko Matsudai ,  Yuichi Goto

IPC分类号： H01L29/78 ,  H01L21/761 ,  H01L29/739 ,  H01L29/66 ,  H01L29/861 ,  H01L29/06 ,  H01L29/10

CPC分类号： H01L21/761 ,  H01L29/0696 ,  H01L29/1095 ,  H01L29/66128 ,  H01L29/7394 ,  H01L29/7824 ,  H01L29/8611 ,  Y10S257/91

摘要： According to one embodiment, in a dielectric isolation substrate, an insulating film having a first thickness is provided on a semiconductor substrate. A semiconductor layer of a first conductivity type having a second thickness is provided on the insulating film. An impurity diffusion layer of a second conductivity type is provided partially in a lower portion of the semiconductor layer and is in contact with the insulating film.

摘要翻译： 根据一个实施例，在绝缘隔离衬底中，在半导体衬底上设置具有第一厚度的绝缘膜。 具有第二厚度的第一导电类型的半导体层设置在绝缘膜上。 第二导电类型的杂质扩散层部分地设置在半导体层的下部并与绝缘膜接触。

公开(公告)号：US08643095B2

公开(公告)日：2014-02-04

申请号：US13239248

申请日：2011-09-21

申请人： Miwako Suzuki ,  Norio Yasuhara

发明人： Miwako Suzuki ,  Norio Yasuhara

IPC分类号： H01L29/66

CPC分类号： H01L29/7813 ,  H01L29/0634 ,  H01L29/0878 ,  H01L29/1095 ,  H01L29/407 ,  H01L29/66734

摘要： According to one embodiment, a semiconductor device includes a drift layer. The device includes a base layer. The device includes a source layer selectively provided on a surface of the base layer. The device includes a gate electrode provided via a gate insulating film in a trench penetrating the source layer and the base layer to reach the drift layer. The device includes a field plate electrode provided under the gate electrode in the trench. The device includes a drain electrode electrically connected to the drift layer. The device includes a source electrode. The field plate electrode is electrically connected to the source electrode. An impurity concentration of a first conductivity type contained in the base layer is lower than an impurity concentration of the first conductivity type contained in the drift layer. And the impurity concentration of the first conductivity type contained in the drift layer is not less than 1×1016 (atoms/cm3).

摘要翻译： 根据一个实施例，半导体器件包括漂移层。 该装置包括基层。 该装置包括选择性地设置在基底层的表面上的源极层。 该器件包括通过栅极绝缘膜设置在穿过源极层的沟槽和基极层中以到达漂移层的栅电极。 该器件包括设置在沟槽中的栅电极下方的场板电极。 该器件包括电连接到漂移层的漏电极。 该装置包括源电极。 场极板电极与源电极电连接。 包含在基底层中的第一导电类型的杂质浓度低于漂移层中包含的第一导电类型的杂质浓度。 并且漂移层中所含的第一导电类型的杂质浓度不小于1×1016（原子/ cm3）。

公开(公告)号：US20130049111A1

公开(公告)日：2013-02-28

申请号：US13410739

申请日：2012-03-02

申请人： Ryo WADA ,  Kaori Yoshioka ,  Norio Yasuhara ,  Tomoko Matsudai ,  Yuichi Goto

发明人： Ryo WADA ,  Kaori Yoshioka ,  Norio Yasuhara ,  Tomoko Matsudai ,  Yuichi Goto

IPC分类号： H01L29/78 ,  H01L29/06

CPC分类号： H01L21/761 ,  H01L29/0696 ,  H01L29/1095 ,  H01L29/66128 ,  H01L29/7394 ,  H01L29/7824 ,  H01L29/8611 ,  Y10S257/91

摘要： According to one embodiment, in a dielectric isolation substrate, an insulating film having a first thickness is provided on a semiconductor substrate. A semiconductor layer of a first conductivity type having a second thickness is provided on the insulating film. An impurity diffusion layer of a second conductivity type is provided partially in a lower portion of the semiconductor layer and is in contact with the insulating film.

摘要翻译： 根据一个实施例，在绝缘隔离衬底中，在半导体衬底上设置具有第一厚度的绝缘膜。 具有第二厚度的第一导电类型的半导体层设置在绝缘膜上。 第二导电类型的杂质扩散层部分地设置在半导体层的下部并与绝缘膜接触。

公开(公告)号：US08362554B2

公开(公告)日：2013-01-29

申请号：US12878979

申请日：2010-09-09

申请人： Tomoko Matsudai ,  Norio Yasuhara ,  Takashi Tsurugai ,  Kumiko Sato

发明人： Tomoko Matsudai ,  Norio Yasuhara ,  Takashi Tsurugai ,  Kumiko Sato

IPC分类号： H01L29/78

CPC分类号： H01L29/0692 ,  H01L29/1087 ,  H01L29/66659 ,  H01L29/7835

摘要： According to one embodiment, a semiconductor device includes a drain region, a source region, a channel region, an insulating film, a gate electrode, a first semiconductor region, and a second semiconductor region. The source region includes a source layer of the first conductivity type, a first back gate layer of the second conductivity type, and a second back gate layer of the second conductivity type. The first back gate layer is adjacent to the second semiconductor region on one side in a channel length direction, and is adjacent to the source layer on one other side in the channel length direction. The second back gate layer is adjacent to the source layer on the one side in the channel length direction, and is adjacent to the second semiconductor region on the one other side in the channel length direction.

摘要翻译： 根据一个实施例，半导体器件包括漏极区，源极区，沟道区，绝缘膜，栅电极，第一半导体区和第二半导体区。 源极区包括第一导电类型的源极层，第二导电类型的第一背栅极层和第二导电类型的第二背栅极层。 第一背栅层在沟道长度方向的一侧与第二半导体区相邻，并且在沟道长度方向的另一侧与源极相邻。 第二背栅层在沟道长度方向的一侧与源极层相邻，并且与沟道长度方向的另一侧的第二半导体区域相邻。

公开(公告)号：US20110133818A1

公开(公告)日：2011-06-09

申请号：US13022611

申请日：2011-02-07

申请人： Tomoko MATSUDAI ,  Norio Yasuhara ,  Kazutoshi Nakamura

发明人： Tomoko MATSUDAI ,  Norio Yasuhara ,  Kazutoshi Nakamura

IPC分类号： H03K3/01 ,  H01L29/78

CPC分类号： H01L29/7835 ,  H01L21/266 ,  H01L29/0847 ,  H01L29/1045 ,  H01L29/1083 ,  H01L29/1087 ,  H01L29/66659

摘要： A semiconductor device includes a semiconductor layer of a first conductivity type; a deep well of a second conductivity type formed in a portion of an upper layer portion of the semiconductor layer; a well of the first conductivity type formed in a portion of an upper layer portion of the deep well; a source layer of the second conductivity type formed in the well; a drain layer of the second conductivity type formed in the well apart from the source layer; and a contact layer of the second conductivity type formed outside the well in an upper layer portion of the deep well and connected to the drain layer. The drain layer is electrically connected to the deep well via the well by applying a driving voltage between the source layer and the drain layer.

摘要翻译： 半导体器件包括第一导电类型的半导体层; 形成在半导体层的上层部分的一部分中的第二导电类型的深阱; 形成在深井的上层部分的一部分中的第一导电类型的阱; 在井中形成的第二导电类型的源极层; 第二导电类型的漏极层形成在远离源极的阱中; 以及在阱的上层部分中形成在阱外部并连接到漏极层的第二导电类型的接触层。 通过在源极层和漏极层之间施加驱动电压，漏极层通过阱与深阱电连接。

公开(公告)号：US20090065862A1

公开(公告)日：2009-03-12

申请号：US12264580

申请日：2008-11-04

申请人： Tomoko MATSUDAI ,  Norio Yasuhara

发明人： Tomoko MATSUDAI ,  Norio Yasuhara

IPC分类号： H01L29/78

CPC分类号： H01L29/7816 ,  H01L29/063 ,  H01L29/0878 ,  H01L29/1045 ,  H01L29/1083 ,  H01L29/1095 ,  H01L29/66681 ,  H01L29/7835 ,  H01L2924/0002 ,  H01L2924/00

摘要： A semiconductor device comprising: a base layer of a first conductivity type selectively formed above a semiconductor substrate; a gate electrode formed on the base layer via the insulating film; a source layer of a second conductivity type selectively formed at a surface of the base layer at one side of the gate electrode; an channel implantation layer selectively formed at the surface of the base layer so as to be adjacent to the source layer below the gate electrode, the channel implantation layer having a higher concentration than the base layer; a RESURF layer of the second conductivity type selectively formed at the surface of the base layer at the other side of the gate electrode; and a drain layer of a second conductivity type being adjacent to the RESURF layer, a portion of the drain layer overlapping the base layer, and the drain layer having a higher concentration than the RESURF layer.

摘要翻译： 一种半导体器件，包括：选择性地形成在半导体衬底之上的第一导电类型的基极层; 经由所述绝缘膜形成在所述基底层上的栅电极; 选择性地形成在所述基极层的所述栅电极的一侧的表面处的第二导电类型的源极层; 沟道注入层，其选择性地形成在所述基底层的表面处以与所述栅极电极下方的源极层相邻，所述沟道注入层具有比所述基底层更高的浓度; 所述第二导电类型的RESURF层选择性地形成在所述基极层的所述栅极电极的另一侧的表面处; 以及与RESURF层相邻的第二导电类型的漏极层，所述漏极层的一部分与所述基极层重叠，并且所述漏极层具有比所述RESURF层更高的浓度。

公开(公告)号：US20080315305A1

公开(公告)日：2008-12-25

申请号：US12141386

申请日：2008-06-18

申请人： Tomoko Matsudai ,  Norio Yasuhara ,  Manji Obatake

发明人： Tomoko Matsudai ,  Norio Yasuhara ,  Manji Obatake

IPC分类号： H01L29/78 ,  H01L21/336

CPC分类号： H01L29/0847 ,  H01L21/2652 ,  H01L21/2658 ,  H01L29/42376 ,  H01L29/66659 ,  H01L29/7835

摘要： A LDD layer of the second conduction type locates in the surface of a semiconductor layer beneath a sidewall insulator film. A source layer of the second conduction type is formed in the surface of the semiconductor layer at a position adjacent to the LDD layer. A resurf layer of the second conduction type is formed in the surface of the semiconductor layer at a position sandwiching the gate electrode with the LDD layer. A drain layer of the second conduction type is formed in the surface of the semiconductor layer at a position adjacent to the resurf layer. The resurf layer is formed in depth to have peaks of a first and a second impurity concentration in turn from the surface of the semiconductor layer. The peak of the first impurity concentration is smaller than the peak of the second impurity concentration.

摘要翻译： 第二导电类型的LDD层位于侧壁绝缘膜下面的半导体层的表面。 第二导电类型的源极层在与LDD层相邻的位置处形成在半导体层的表面中。 在半导体层的表面上，在与LDD层夹着栅电极的位置处形成第二导电类型的复层。 第二导电类型的漏极层在与复层层相邻的位置处形成在半导体层的表面中。 再次形成深度为半导体层表面的第一和第二杂质浓度的峰值。 第一杂质浓度的峰值小于第二杂质浓度的峰值。

公开(公告)号：US20080251838A1

公开(公告)日：2008-10-16

申请号：US12118159

申请日：2008-05-09

申请人： Syotaro Ono ,  Yoshihiro Yamaguchi ,  Yusuke Kawaguchi ,  Kazutoshi Nakamura ,  Norio Yasuhara ,  Kenichi Matsushita ,  Shinichi Hodama ,  Akio Nakagawa

发明人： Syotaro Ono ,  Yoshihiro Yamaguchi ,  Yusuke Kawaguchi ,  Kazutoshi Nakamura ,  Norio Yasuhara ,  Kenichi Matsushita ,  Shinichi Hodama ,  Akio Nakagawa

IPC分类号： H01L29/78

CPC分类号： H01L29/7802 ,  H01L21/26586 ,  H01L29/0653 ,  H01L29/0696 ,  H01L29/0847 ,  H01L29/0878 ,  H01L29/1095 ,  H01L29/402 ,  H01L29/407 ,  H01L29/42368 ,  H01L29/42376 ,  H01L29/4238 ,  H01L29/66712 ,  H01L29/7809

摘要： A semiconductor device includes: a semiconductor substrate, at least a surface portion thereof serving as a low-resistance drain layer of a first conductivity type; a first main electrode connected to the low-resistance drain layer; a high-resistance epitaxial layer of a second-conductivity type formed on the low-resistance drain layer; a second-conductivity type base layer selectively formed on the high-resistance epitaxial layer; a first-conductivity type source layer selectively formed in a surface portion of the second-conductivity type base layer; a trench formed in a region sandwiched by the second-conductivity type base layers with a depth extending from the surface of the high-resistance epitaxial layer to the semiconductor substrate; a jfet layer of the first conductivity type formed on side walls of the trench; an insulating layer formed in the trench; an LDD layer of the first-conductivity type formed in a surface portion of the second-conductivity type base layer so as to be connected to the first-conductivity type jfet layer around a top face of the trench; a control electrode formed above the semiconductor substrate so as to be divided into a plurality of parts, and formed on a gate insulating film formed on a part of the surface of the LDD layer, on surfaces of end parts of the first-conductivity type source layer facing each other across the trench, and on a region of the surface of the second-conductivity type base layer sandwiched by the LDD layer and the first-conductivity type source layer; and a second main electrode in ohmic contact with the first-conductivity type source layer and the second-conductivity type base layer so as to sandwich the control electrode.

摘要翻译： 半导体器件包括：半导体衬底，至少其表面部分用作第一导电类型的低电阻漏极层; 连接到所述低电阻漏极层的第一主电极; 形成在低电阻漏极层上的第二导电类型的高电阻外延层; 选择性地形成在高电阻外延层上的第二导电型基极层; 选择性地形成在所述第二导电型基底层的表面部分中的第一导电型源极层; 在由所述第二导电型基底层夹持的区域中形成的沟槽，其深度从所述高电阻外延层的表面延伸到所述半导体衬底; 形成在沟槽的侧壁上的第一导电类型的jfet层; 形成在沟槽中的绝缘层; 形成在第二导电型基底层的表面部分中的第一导电类型的LDD层，以便围绕沟槽的顶面连接到第一导电型jfet层; 控制电极，其形成在所述半导体衬底上，以被分成多个部分，并形成在形成在所述LDD层的一部分表面上的栅极绝缘膜上，所述第一导电型源的端部 并且在由LDD层和第一导电型源极层夹在第二导电型基底层的表面的区域上， 以及与所述第一导电型源极层和所述第二导电型基极欧姆接触以便夹持所述控制电极的第二主电极。