公开(公告)号：US20120026798A1

公开(公告)日：2012-02-02

申请号：US13269425

申请日：2011-10-07

申请人： Digh HISAMOTO ,  Kan Yasui ,  Tetsuya Ishimaru ,  Shinichiro Kimura ,  Daisuke Okada

发明人： Digh HISAMOTO ,  Kan Yasui ,  Tetsuya Ishimaru ,  Shinichiro Kimura ,  Daisuke Okada

IPC分类号： G11C16/10

CPC分类号： G11C16/0425 ,  G11C16/12 ,  G11C16/14 ,  G11C16/26 ,  G11C16/3454 ,  G11C16/3459

摘要： An operation scheme for operating stably a semiconductor nonvolatile memory device is provided.When hot-hole injection is conducted in the semiconductor nonvolatile memory device of a split gate structure, the hot-hole injection is verified using a crossing point that does not change with time. Thus, an erased state can be verified without being aware of any time-varying changes.Also, programming or programming/erasure is conducted by repeating pulse voltage or multi-step voltage application to a gate section multiple times.

摘要翻译： 提供一种稳定运行半导体非易失性存储器件的操作方案。 当在分裂栅极结构的半导体非易失性存储器件中进行热空穴注入时，使用不随时间变化的交叉点来验证热孔注入。 因此，可以验证擦除状态，而不知道任何时变变化。 此外，通过将多次脉冲电压或多级电压施加到栅极部分进行编程或编程/擦除。

公开(公告)号：US08076709B2

公开(公告)日：2011-12-13

申请号：US12873679

申请日：2010-09-01

申请人： Tetsuya Ishimaru ,  Digh Hisamoto ,  Kan Yasui ,  Shinichiro Kimura

发明人： Tetsuya Ishimaru ,  Digh Hisamoto ,  Kan Yasui ,  Shinichiro Kimura

IPC分类号： H01L29/792 ,  G11C16/04

CPC分类号： G11C16/0466 ,  H01L21/28282 ,  H01L29/66833 ,  H01L29/792

摘要： In a situation where a memory cell includes an ONO film, which comprises a silicon nitride film for charge storage and oxide films positioned above and below the silicon nitride film; a memory gate above the ONO film; a select gate, which is adjacent to a lateral surface of the memory gate via the ONO film; a gate insulator positioned below the select gate; a source region; and a drain region, an erase operation is performed by injecting holes generated by BTBT into the silicon nitride film while applying a positive potential to the source region, applying a negative potential to the memory gate, applying a positive potential to the select gate, and flowing a current from the drain region to the source region, thus improving the characteristics of a nonvolatile semiconductor memory device.

摘要翻译： 在存储单元包括ONO膜的情况下，其包括用于电荷存储的氮化硅膜和位于氮化硅膜上方和下方的氧化膜; 在ONO电影上方的记忆门; 选择栅极，其经由ONO膜与存储栅的侧表面相邻; 位于选择门下方的栅极绝缘体; 源区; 和漏极区域，通过将BTBT产生的空穴注入氮化硅膜，同时向源极区域施加正电位，向存储栅极施加负电位，向选择栅极施加正电位，进行擦除操作，以及 使电流从漏极区域流向源极区域，从而改善非易失性半导体存储器件的特性。

公开(公告)号：US08064261B2

公开(公告)日：2011-11-22

申请号：US12787158

申请日：2010-05-25

申请人： Digh Hisamoto ,  Kan Yasui ,  Tetsuya Ishimaru ,  Shinichiro Kimura ,  Daisuke Okada

发明人： Digh Hisamoto ,  Kan Yasui ,  Tetsuya Ishimaru ,  Shinichiro Kimura ,  Daisuke Okada

IPC分类号： G11C11/34 ,  G11C16/04 ,  G11C16/06

CPC分类号： G11C16/0425 ,  G11C16/12 ,  G11C16/14 ,  G11C16/26 ,  G11C16/3454 ,  G11C16/3459

摘要： An operation scheme for operating stably a semiconductor nonvolatile memory device is provided.When hot-hole injection is conducted in the semiconductor nonvolatile memory device of a split gate structure, the hot-hole injection is verified using a crossing point that does not change with time. Thus, an erased state can be verified without being aware of any time-varying changes.Also, programming or programming/erasure is conducted by repeating pulse voltage or multi-step voltage application to a gate section multiple times.

摘要翻译： 提供一种稳定运行半导体非易失性存储器件的操作方案。 当在分裂栅结构的半导体非易失性存储器件中进行热孔注入时，使用不随时间变化的交叉点来验证热孔注入。 因此，可以验证擦除状态，而不知道任何时变变化。 此外，通过将多次脉冲电压或多级电压施加到栅极部分进行编程或编程/擦除。

公开(公告)号：US07863131B2

公开(公告)日：2011-01-04

申请号：US11189078

申请日：2005-07-26

申请人： Kan Yasui ,  Digh Hisamoto ,  Tetsuya Ishimaru

发明人： Kan Yasui ,  Digh Hisamoto ,  Tetsuya Ishimaru

IPC分类号： H01L21/336

CPC分类号： H01L29/792 ,  G11C16/0466 ,  H01L27/115 ,  H01L27/11519 ,  H01L27/11568 ,  H01L29/42344

摘要： Semiconductor device and manufacturing method for reducing the number of required lithography masks added to the nonvolatile memory in the standard CMOS process to shorten the production period and reduce costs. In a split-gate memory cell with silicided gate electrodes utilizing a sidewall structure, a separate auxiliary pattern is formed adjoining the selected gate electrodes. A contact is set on a wiring layer self-aligned by filling side-wall gates of polysilicon in the gap between the electrodes and auxiliary pattern. The contact may overlap onto the auxiliary pattern and device isolation region, in an optimal design considering the size of the occupied surface area. If the distance to the selected gate electrode is x, the ONO film deposit thickness is t, and the polysilicon film deposit thickness is d, then the auxiliary pattern may be separated just by a distance x such that x

摘要翻译： 用于减少在标准CMOS工艺中添加到非易失性存储器中的所需光刻掩模的数量的半导体器件和制造方法，以缩短生产周期并降低成本。 在具有利用侧壁结构的硅化栅电极的分裂栅极存储单元中，形成邻接所选择的栅电极的单独辅助图案。 通过填充电极和辅助图案之间的间隙中的多晶硅的侧壁栅极，将接触设置在自对准的布线层上。 考虑到占用的表面积的大小，接触可以以最佳设计重叠在辅助图案和设备隔离区域上。 如果与选定的栅电极的距离为x，则ONO膜沉积厚度为t，多晶硅膜沉积厚度为d，则辅助图案可以仅分开距离x，使得x <2×（t + d ）。

公开(公告)号：US07847331B2

公开(公告)日：2010-12-07

申请号：US11030900

申请日：2005-01-10

申请人： Tetsuya Ishimaru ,  Digh Hisamoto ,  Kan Yasui ,  Shinichiro Kimura

发明人： Tetsuya Ishimaru ,  Digh Hisamoto ,  Kan Yasui ,  Shinichiro Kimura

IPC分类号： H01L29/792

CPC分类号： G11C16/0466 ,  H01L21/28282 ,  H01L29/66833 ,  H01L29/792

摘要： In a situation where a memory cell includes an ONO film, which comprises a silicon nitride film for charge storage and oxide films positioned above and below the silicon nitride film; a memory gate above the ONO film; a select gate, which is adjacent to a lateral surface of the memory gate via the ONO film; a gate insulator positioned below the select gate; a source region; and a drain region, an erase operation is performed by injecting holes generated by BTBT into the silicon nitride film while applying a positive potential to the source region, applying a negative potential to the memory gate, applying a positive potential to the select gate, and flowing a current from the drain region to the source region, thus improving the characteristics of a nonvolatile semiconductor memory device.

摘要翻译： 在存储单元包括ONO膜的情况下，其包括用于电荷存储的氮化硅膜和位于氮化硅膜上方和下方的氧化膜; 在ONO电影上方的记忆门; 选择栅极，其经由ONO膜与存储栅的侧表面相邻; 位于选择门下方的栅极绝缘体; 源区; 和漏极区域，通过将BTBT产生的空穴注入氮化硅膜，同时向源极区域施加正电位，向存储栅极施加负电位，向选择栅极施加正电位，进行擦除操作，以及 使电流从漏极区域流向源极区域，从而改善非易失性半导体存储器件的特性。

公开(公告)号：US07667259B2

公开(公告)日：2010-02-23

申请号：US11452256

申请日：2006-06-14

申请人： Kan Yasui ,  Digh Hisamoto ,  Tetsuya Ishimaru ,  Shin-Ichiro Kimura

发明人： Kan Yasui ,  Digh Hisamoto ,  Tetsuya Ishimaru ,  Shin-Ichiro Kimura

IPC分类号： H01L21/00

CPC分类号： H01L27/115 ,  G11C16/0425 ,  H01L27/11568 ,  H01L29/42344

摘要： A method of manufacturing a non-volatile semiconductor memory device is provided which overcomes a problem of penetration of implanted ions due to the difference of an optimal gate height in simultaneous formation of a self-align split gate type memory cell utilizing a side wall structure and a scaled MOS transistor. A select gate electrode to form a side wall in a memory area is formed to be higher than that of the gate electrode in a logic area so that the height of the side wall gate electrode of the self-align split gate memory cell is greater than that of the gate electrode in the logic area. Height reduction for the gate electrode is performed in the logic area before gate electrode formation.

摘要翻译： 提供了一种制造非易失性半导体存储器件的方法，其克服了由于利用侧壁结构同时形成自对准分裂栅型存储单元而产生的最佳栅极高度的差异而引入的注入离子的问题，以及 一个缩放的MOS晶体管。 形成在存储区域中形成侧壁的选择栅电极比逻辑区域中的栅电极高，使得自对准分离栅极存储单元的侧壁栅电极的高度大于 在逻辑区域的栅电极。 栅极电极的高度降低在栅电极形成之前的逻辑区域中进行。

公开(公告)号：US07443731B2

公开(公告)日：2008-10-28

申请号：US11727592

申请日：2007-03-27

申请人： Digh Hisamoto ,  Kan Yasui ,  Tetsuya Ishimaru ,  Shinichiro Kimura ,  Daisuke Okada

发明人： Digh Hisamoto ,  Kan Yasui ,  Tetsuya Ishimaru ,  Shinichiro Kimura ,  Daisuke Okada

IPC分类号： G11C11/34 ,  G11C16/04

CPC分类号： G11C16/0425 ,  G11C16/12 ,  G11C16/14 ,  G11C16/26 ,  G11C16/3454 ,  G11C16/3459

摘要： An operation scheme for operating stably a semiconductor nonvolatile memory device is provided.When hot-hole injection is conducted in the semiconductor nonvolatile memory device of a split gate structure, the hot-hole injection is verified using a crossing point that does not change with time. Thus, an erased state can be verified without being aware of any time-varying changes.Also, programming or programming/erasure is conducted by repeating pulse voltage or multi-step voltage application to a gate section multiple times.

摘要翻译： 提供一种稳定运行半导体非易失性存储器件的操作方案。 当在分裂栅极结构的半导体非易失性存储器件中进行热空穴注入时，使用不随时间变化的交叉点来验证热孔注入。 因此，可以验证擦除状态，而不知道任何时变变化。 此外，通过将多次脉冲电压或多级电压施加到栅极部分进行编程或编程/擦除。

公开(公告)号：US20060234454A1

公开(公告)日：2006-10-19

申请号：US11404899

申请日：2006-04-17

申请人： Kan Yasui ,  Shinichiro Kimura ,  Digh Hisamoto ,  Tetsuya Ishimaru

发明人： Kan Yasui ,  Shinichiro Kimura ,  Digh Hisamoto ,  Tetsuya Ishimaru

IPC分类号： H01L21/336

CPC分类号： H01L29/792 ,  G11C16/0425 ,  G11C16/0466 ,  H01L27/105 ,  H01L27/11568 ,  H01L29/40117 ,  H01L29/42344 ,  H01L29/66833

摘要： After forming a first dielectric film on the main surface of a semiconductor substrate, a first conductive film is formed on the first dielectric film, and then, the surface of the first conductive film is planarized by a CMP method. Subsequently, the first conductive film and the first dielectric film are etched, thereby forming a select gate having a first gate electrode and a first gate dielectric film. Subsequently, after forming a second dielectric film on the sidewall of the first gate electrode and the main surface, a second conductive film is formed on the second dielectric film, and the second conductive film is etched, thereby forming a memory gate having a second gate electrode and a second gate dielectric film.

摘要翻译： 在半导体衬底的主表面上形成第一电介质膜之后，在第一电介质膜上形成第一导电膜，然后通过CMP方法将第一导电膜的表面平坦化。 随后，蚀刻第一导电膜和第一电介质膜，从而形成具有第一栅极电极和第一栅极电介质膜的选择栅极。 随后，在第一栅电极和主表面的侧壁上形成第二电介质膜之后，在第二电介质膜上形成第二导电膜，并且蚀刻第二导电膜，从而形成具有第二栅极的存储栅极 电极和第二栅极电介质膜。

公开(公告)号：US20050230736A1

公开(公告)日：2005-10-20

申请号：US11030900

申请日：2005-01-10

申请人： Tetsuya Ishimaru ,  Digh Hisamoto ,  Kan Yasui ,  Shinichiro Kimura

发明人： Tetsuya Ishimaru ,  Digh Hisamoto ,  Kan Yasui ,  Shinichiro Kimura

IPC分类号： G11C16/02 ,  G11C16/04 ,  H01L21/28 ,  H01L21/336 ,  H01L21/8247 ,  H01L27/105 ,  H01L27/115 ,  H01L29/78 ,  H01L29/788 ,  H01L29/792

CPC分类号： G11C16/0466 ,  H01L21/28282 ,  H01L29/66833 ,  H01L29/792

摘要： In a situation where a memory cell includes an ONO film, which comprises a silicon nitride film for charge storage and oxide films positioned above and below the silicon nitride film; a memory gate above the ONO film; a select gate, which is adjacent to a lateral surface of the memory gate via the ONO film; a gate insulator positioned below the select gate; a source region; and a drain region, an erase operation is performed by injecting holes generated by BTBT into the silicon nitride film while applying a positive potential to the source region, applying a negative potential to the memory gate, applying a positive potential to the select gate, and flowing a current from the drain region to the source region, thus improving the characteristics of a nonvolatile semiconductor memory device.

摘要翻译： 在存储单元包括ONO膜的情况下，其包括用于电荷存储的氮化硅膜和位于氮化硅膜上方和下方的氧化膜; 在ONO电影上方的记忆门; 选择栅极，其经由ONO膜与存储栅的侧表面相邻; 位于选择门下方的栅极绝缘体; 源区; 和漏极区域，通过将BTBT产生的空穴注入氮化硅膜，同时向源极区域施加正电位，向存储栅极施加负电位，向选择栅极施加正电位，进行擦除操作，以及 使电流从漏极区域流向源极区域，从而改善非易失性半导体存储器件的特性。

公开(公告)号：US20100105199A1

公开(公告)日：2010-04-29

申请号：US12652517

申请日：2010-01-05

申请人： Kan Yasui ,  Digh Hisamoto ,  Tetsuya Ishimaru ,  Shin-Ichiro Kimura

发明人： Kan Yasui ,  Digh Hisamoto ,  Tetsuya Ishimaru ,  Shin-Ichiro Kimura

IPC分类号： H01L21/28

CPC分类号： H01L27/115 ,  G11C16/0425 ,  H01L27/11568 ,  H01L29/42344

摘要： A method of manufacturing a non-volatile semiconductor memory device is provided which overcomes a problem of penetration of implanted ions due to the difference of optimal gate height in simultaneous formation of a self-align split gate type memory cell utilizing a side wall structure and a scaled MOS transistor. A select gate electrode to form a side wall in a memory area is formed to be higher than that of the gate electrode in a logic area so that the height of the side wall gate electrode of the self-align split gate memory cell is greater than that of the gate electrode in the logic area. Height reduction for the gate electrode is performed in the logic area before gate electrode formation.

摘要翻译： 提供一种制造非挥发性半导体存储器件的方法，其克服了由于最佳栅极高度的不同而引入的注入离子的问题，同时形成利用侧壁结构的自对准分裂栅型存储单元和 缩放MOS晶体管。 形成在存储区域中形成侧壁的选择栅电极比逻辑区域中的栅电极高，使得自对准分离栅极存储单元的侧壁栅电极的高度大于 在逻辑区域的栅电极。 栅极电极的高度降低在栅电极形成之前的逻辑区域中进行。