公开(公告)号：US20250117038A1

公开(公告)日：2025-04-10

申请号：US18983491

申请日：2024-12-17

Applicant: Texas Instruments Incorporated

Inventor： Shailesh Ghotgalkar ,  Rajeev Suvarna ,  Prasanth Viswanathan Pillai ,  Saravanan G

IPC: G06F1/08 ,  G06F1/12 ,  G06F11/16 ,  H03K5/135 ,  H03K5/26

Abstract: An example device comprising: first clock divider circuitry to be coupled to a first clock; first counter circuitry configured to be coupled to the first clock divider circuitry, the first counter circuitry configured to increment based on the first clock and a second clock; second clock divider circuitry to be coupled to a third clock; second counter circuitry configured to be coupled to the second clock divider circuitry, the second counter circuitry configured to increment based on the third clock and the second clock; and comparison circuitry coupled to the first and second counter circuitry.

公开(公告)号：US12025659B2

公开(公告)日：2024-07-02

申请号：US18047511

申请日：2022-10-18

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Prasanth Viswanathan Pillai ,  Rajeev Suvarna ,  Saya Goud Langadi ,  Shailesh Ganapat Ghotgalkar

IPC: G06F3/06 ,  G01R31/3177 ,  G01R31/3185 ,  G01R31/3187 ,  G06F11/10 ,  G06F12/0804 ,  G06F13/16 ,  H03K3/037 ,  H03K5/24 ,  H03K19/003

CPC classification number: G01R31/3177 ,  G01R31/3187 ,  H03K3/037 ,  H03K5/24 ,  H03K19/003 ,  G01R31/318566

Abstract: Lockstep comparators and related methods are described. An example apparatus includes self-test logic circuitry having first outputs, and comparator logic including selection logic having first inputs and second outputs, ones of the first inputs coupled to the first outputs, first detection logic having second inputs and third outputs, the second inputs coupled to the second outputs, second detection logic having third inputs and fourth outputs, the third inputs coupled to the third outputs, latch logic having fifth inputs and fifth outputs, the third output and the fourth output coupled to the fifth inputs, and error detection logic having sixth inputs coupled to the fifth inputs.

公开(公告)号：US20220206065A1

公开(公告)日：2022-06-30

申请号：US17138529

申请日：2020-12-30

Applicant: Texas Instruments Incorporated

Inventor： Prasanth Viswanathan Pillai ,  Rajeev Suvarna ,  Saya Goud Langadi ,  Shailesh Ganapat Ghotgalkar

IPC: G01R31/3177 ,  H03K3/037 ,  H03K19/003 ,  H03K5/24

Abstract: Lockstep comparators and related methods are described. An example apparatus includes self-test logic circuitry having first outputs, and comparator logic including selection logic having first inputs and second outputs, ones of the first inputs coupled to the first outputs, first detection logic having second inputs and third outputs, the second inputs coupled to the second outputs, second detection logic having third inputs and fourth outputs, the third inputs coupled to the third outputs, latch logic having fifth inputs and fifth outputs, the third output and the fourth output coupled to the fifth inputs, and error detection logic having sixth inputs coupled to the fifth inputs.

公开(公告)号：US10014041B1

公开(公告)日：2018-07-03

申请号：US15389814

申请日：2016-12-23

Applicant: Texas Instruments Incorporated

Inventor： Nikunj Khare ,  Rajeev Suvarna ,  Gregory A. North ,  Maneesh Soni

IPC: G11C7/22 ,  G11C7/10

Abstract: Disclosed examples include interface circuits to transfer data between a first register in a fast clock domain and a second register in a slow clock domain, including a resettable synchronizer to provide a synchronized start signal synchronized to a slow clock signal to initiate a write from the first register to the second register according to a write request signal, a pulse generator circuit to provide a write enable pulse signal according to the synchronized start signal, a write control circuit to selectively connect an output of the first register to an input of the second register to write data from the first register to the second register according to the write enable pulse signal, and a dual flip-flop to provide a reset signal synchronized to a fast clock signal according to the write request signal to clear any prior pending write request and begin a new write operation.

公开(公告)号：US20230213958A1

公开(公告)日：2023-07-06

申请号：US17892860

申请日：2022-08-22

Applicant: Texas Instruments Incorporated

Inventor： Shailesh Ghotgalkar ,  Rajeev Suvarna ,  Prasanth Viswanathan Pillai ,  Saravanan G

IPC: G06F1/08 ,  G06F1/12 ,  H03K5/26 ,  H03K5/135

CPC classification number: G06F1/08 ,  G06F1/12 ,  H03K5/26 ,  H03K5/135

Abstract: An example device comprising: first clock divider circuitry to be coupled to a first clock; first counter circuitry configured to be coupled to the first clock divider circuitry, the first counter circuitry configured to increment based on the first clock and a second clock; second clock divider circuitry to be coupled to a third clock; second counter circuitry configured to be coupled to the second clock divider circuitry, the second counter circuitry configured to increment based on the third clock and the second clock; and comparison circuitry coupled to the first and second counter circuitry.

公开(公告)号：US20230068811A1

公开(公告)日：2023-03-02

申请号：US18047511

申请日：2022-10-18

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Prasanth Viswanathan Pillai ,  Rajeev Suvarna ,  Saya Goud Langadi ,  Shailesh Ganapat Ghotgalkar

IPC: G01R31/3177 ,  H03K5/24 ,  H03K19/003 ,  H03K3/037

Abstract: Lockstep comparators and related methods are described. An example apparatus includes self-test logic circuitry having first outputs, and comparator logic including selection logic having first inputs and second outputs, ones of the first inputs coupled to the first outputs, first detection logic having second inputs and third outputs, the second inputs coupled to the second outputs, second detection logic having third inputs and fourth outputs, the third inputs coupled to the third outputs, latch logic having fifth inputs and fifth outputs, the third output and the fourth output coupled to the fifth inputs, and error detection logic having sixth inputs coupled to the fifth inputs.

公开(公告)号：US10788853B2

公开(公告)日：2020-09-29

申请号：US15420267

申请日：2017-01-31

Applicant: Texas Instruments Incorporated

Inventor： Maneesh Soni ,  Rajeev Suvarna ,  Nikunj Khare

IPC: G06F1/12 ,  G06F13/24

Abstract: Disclosed examples include interrupt handling circuitry and methods for managing interrupts of a fast clock domain circuit operated according to a first clock signal by a slow clock domain circuit operated according to a second clock signal in which an interrupt generator circuit generates an interrupt input signal synchronized to the second clock signal, and an interrupt clear circuit selectively resets the interrupt generator circuit in response to an acknowledgment signal from the first circuit asynchronously with respect to the second clock signal.

公开(公告)号：US10095474B2

公开(公告)日：2018-10-09

申请号：US14270165

申请日：2014-05-05

Applicant: Texas Instruments Incorporated

Inventor： Rakesh Yaraduyathinahalli Channabasappa ,  Shekhar Dinkar Patil ,  Rajeev Suvarna

IPC: G06F3/06 ,  G06F5/10 ,  G11C8/16

Abstract: An apparatus includes a controller and logic circuitry. The controller is configured to generate multiple single-bit logic values. Each single-bit logic value has one of (i) a first value indicating that a data packet has been written into a memory and (ii) a second value indicating that a data packet has been read from the memory. The logic circuitry is configured to serially stack the single-bit logic values. The apparatus could further include a shift memory bank configured to store the single-bit logic values. The logic circuitry can be configured to serially stack the single-bit logic values in the shift memory bank. For example, the logic circuitry can be configured to shift the single-bit logic values in the shift memory bank in different directions and insert one single-bit logic value into the memory bank at different ends depending on whether the one logic value has the first or second value.

公开(公告)号：US09489332B2

公开(公告)日：2016-11-08

申请号：US14827077

申请日：2015-08-14

Applicant: Texas Instruments Incorporated

Inventor： Balatripura Sodemma Chavali ,  Karl Friedrich Greb ,  Rajeev Suvarna

IPC: G06F12/00 ,  G06F13/16 ,  G06F13/40 ,  G06F12/14 ,  G06F13/42

CPC classification number: G06F13/4068 ,  G06F12/1416 ,  G06F12/1458 ,  G06F12/1483 ,  G06F13/1605 ,  G06F13/4221 ,  G06F2212/1016 ,  G06F2212/1052

Abstract: A memory protection unit including hardware logic. The hardware logic receives a transaction from a virtual central processing unit (CPU) directed at a bus slave, the transaction being associated with a virtual CPU identification (ID), wherein the virtual CPU is implemented on a physical CPU. The hardware logic also determines whether to grant or deny access to the bus slave based on the virtual CPU ID. The virtual CPU ID is different than an ID of the physical CPU on which the virtual CPU is implemented.

公开(公告)号：US20150356046A1

公开(公告)日：2015-12-10

申请号：US14827077

申请日：2015-08-14

Applicant: Texas Instruments Incorporated

Inventor： Balatripura Sodemma Chavali ,  Karl Friedrich Greb ,  Rajeev Suvarna

IPC: G06F13/40 ,  G06F13/42

CPC classification number: G06F13/4068 ,  G06F12/1416 ,  G06F12/1458 ,  G06F12/1483 ,  G06F13/1605 ,  G06F13/4221 ,  G06F2212/1016 ,  G06F2212/1052

Abstract: A memory protection unit including hardware logic. The hardware logic receives a transaction from a virtual central processing unit (CPU) directed at a bus slave, the transaction being associated with a virtual CPU identification (ID), wherein the virtual CPU is implemented on a physical CPU. The hardware logic also determines whether to grant or deny access to the bus slave based on the virtual CPU ID. The virtual CPU ID is different than an ID of the physical CPU on which the virtual CPU is implemented.

Abstract translation: 一个包含硬件逻辑的存储器保护单元。 硬件逻辑从针对总线从设备的虚拟中央处理单元（CPU）接收事务，该事务与虚拟CPU标识（ID）相关联，其中虚拟CPU在物理CPU上实现。 硬件逻辑还根据虚拟CPU ID确定是否准予或拒绝对总线从站的访问。 虚拟CPU ID与实现虚拟CPU的物理CPU的ID不同。