公开(公告)号：US09294116B2

公开(公告)日：2016-03-22

申请号：US14643528

申请日：2015-03-10

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Rajendrakumar Joish

IPC: H03M1/44 ,  H03M1/14 ,  H03M1/66 ,  H03M1/12

CPC classification number: H03M1/442 ,  H03M1/06 ,  H03M1/12 ,  H03M1/145 ,  H03M1/66

Abstract: A circuit includes an amplifier circuit that receives a residue voltage from an output capacitor connected to an output of a digital to analog converter (DAC). The DAC is employed in a pipeline stage of an analog to digital converter (ADC). The amplifier circuit provides a scaled output voltage based on the residue voltage. A sample circuit samples the scaled output voltage during a first portion of a hold phase of the DAC. A discharge circuit supplies the sampled scaled output voltage to the output of the DAC during a second portion of the hold phase of the DAC to mitigate settling time of the DAC.

Abstract translation: 电路包括放大器电路，其从连接到数模转换器（DAC）的输出的输出电容器接收残留电压。 DAC用于模数转换器（ADC）的流水线级。 放大器电路基于残余电压提供缩放的输出电压。 在DAC的保持阶段的第一部分期间，采样电路对缩放的输出电压进行采样。 在DAC的保持阶段的第二部分期间，放电电路将采样的缩放输出电压提供给DAC的输出，以减轻DAC的稳定时间。

公开(公告)号：US10581406B2

公开(公告)日：2020-03-03

申请号：US16005673

申请日：2018-06-11

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Jawaharlal Tangudu ,  Karthik Khanna S ,  Chandrasekhar Sriram ,  Rajendrakumar Joish ,  Viswanathan Nagarajan

IPC: H03H11/12 ,  H01P1/22 ,  H03H11/06 ,  H03H11/04 ,  H03M1/12

Abstract: A circuit for digital filtering an analog signal converted to digital, including an analog circuit to generate an analog signal, the analog signal including phase and/or gain errors. An analog-to-digital converter (ADC) to convert the analog signal to a digital signal output to a digital signal path. A frequency-dependent corrector filter included in the digital signal path, and configured as a parameterized filter, the parameterized filter configurable based on the DSA control signal with at least one complex filter parameter for each DSA attenuation step, to correct frequency-dependent errors in phase and/or gain.

公开(公告)号：US10263575B2

公开(公告)日：2019-04-16

申请号：US15824984

申请日：2017-11-28

Applicant: Texas Instruments Incorporated

Inventor： Rajendrakumar Joish

IPC: H03F3/68 ,  H03F3/19 ,  H03F1/02 ,  H03F3/191 ,  H03F3/45 ,  H03F1/32 ,  H03F1/22

Abstract: The disclosure provides an amplifier. The amplifier includes a first transistor that receives a first input and generates a first load current. A first output node is coupled to a power supply through a first load resistor. The first load resistor receives the first load current. A first capacitor network is coupled to the first output node and draws a first capacitive current from the first output node. A first current buffer is coupled between the first output node and the first transistor. A current through the first current buffer is a summation of the first load current and the first capacitive current.

公开(公告)号：US10033341B2

公开(公告)日：2018-07-24

申请号：US15464091

申请日：2017-03-20

Applicant: Texas Instruments Incorporated

Inventor： Rajendrakumar Joish

IPC: H03G1/00 ,  H03F3/45 ,  H04B1/10

Abstract: The disclosure provides an amplifier. The amplifier includes a first transistor that receives a first input. A second transistor receives a second input. A plurality of impedance networks is coupled between the first transistor and the second transistor. At least one impedance network of the plurality of impedance networks includes a first impedance path and a second impedance path. The first impedance path is activated during single ended operation, and the second impedance path is activated during differential operation.

公开(公告)号：US09847760B1

公开(公告)日：2017-12-19

申请号：US15620171

申请日：2017-06-12

Applicant: Texas Instruments Incorporated

Inventor： Shagun Dusad ,  Rajendrakumar Joish

IPC: H03M1/12 ,  H03F3/00 ,  G11C27/02 ,  H04B1/40

CPC classification number: H04B1/40 ,  G11C27/026 ,  H03F3/193 ,  H03F3/45188 ,  H03F3/505 ,  H03F2200/451 ,  H03F2203/45514 ,  H03F2203/45551 ,  H03F2203/5024 ,  H03M1/1245

Abstract: The disclosure provides a circuit. The circuit includes a gain stage block. The gain stage block is coupled to an input voltage through a first switch. A first capacitor is coupled between the first switch and a ground terminal. A second capacitor is coupled between the first switch and a second switch. A third switch is coupled between the second capacitor and a fixed terminal of the gain stage block.

公开(公告)号：US09595937B2

公开(公告)日：2017-03-14

申请号：US14854083

申请日：2015-09-15

Applicant: Texas Instruments Incorporated

Inventor： Rajendrakumar Joish

IPC: H03H11/24 ,  H03L5/00 ,  H03H7/25

CPC classification number: H03H7/25

Abstract: Disclosed examples include a programmable attenuator circuit providing selective cross coupling of impedance components between circuit input nodes and output nodes according to control signals to set or adjust an attenuation value of the attenuator circuit. The attenuator circuit includes a plurality of attenuator impedance components, and a switching circuit to selectively connect at least a first attenuator impedance component between the first input node and the second output node, to selectively connect at least a second attenuator impedance component between the second input node and the first output node, to selectively connect a third attenuator impedance component between the first input node and the first output node, and to selectively connect a fourth attenuator impedance component between the second input node and the second output node.

Abstract translation: 公开的示例包括可编程衰减器电路，其根据控制信号提供电路输入节点和输出节点之间的阻抗分量的选择性交叉耦合，以设置或调整衰减器电路的衰减值。 衰减器电路包括多个衰减器阻抗分量，以及切换电路，用于选择性地连接第一输入节点和第二输出节点之间的至少第一衰减器阻抗分量，以选择性地将第二衰减器阻抗分量连接在第二输入端 节点和第一输出节点，以在第一输入节点和第一输出节点之间选择性地连接第三衰减器阻抗分量，并且在第二输入节点和第二输出节点之间选择性地连接第四衰减器阻抗分量。

公开(公告)号：US20160079959A1

公开(公告)日：2016-03-17

申请号：US14854083

申请日：2015-09-15

Applicant: Texas Instruments Incorporated

Inventor： Rajendrakumar Joish

IPC: H03H11/24

CPC classification number: H03H7/25

Abstract: Disclosed examples include a programmable attenuator circuit providing selective cross coupling of impedance components between circuit input nodes and output nodes according to control signals to set or adjust an attenuation value of the attenuator circuit. The attenuator circuit includes a plurality of attenuator impedance components, and a switching circuit to selectively connect at least a first attenuator impedance component between the first input node and the second output node, to selectively connect at least a second attenuator impedance component between the second input node and the first output node, to selectively connect a third attenuator impedance component between the first input node and the first output node, and to selectively connect a fourth attenuator impedance component between the second input node and the second output node.

Abstract translation: 公开的示例包括可编程衰减器电路，其根据控制信号提供电路输入节点和输出节点之间的阻抗分量的选择性交叉耦合，以设置或调整衰减器电路的衰减值。 衰减器电路包括多个衰减器阻抗分量，以及切换电路，用于选择性地连接第一输入节点和第二输出节点之间的至少第一衰减器阻抗分量，以选择性地将第二衰减器阻抗分量连接在第二输入端 节点和第一输出节点，以在第一输入节点和第一输出节点之间选择性地连接第三衰减器阻抗分量，并且在第二输入节点和第二输出节点之间选择性地连接第四衰减器阻抗分量。

公开(公告)号：US20250030390A1

公开(公告)日：2025-01-23

申请号：US18678818

申请日：2024-05-30

Applicant: Texas Instruments Incorporated

Inventor： Vysakh K ,  Shagun Dusad ,  Rajendrakumar Joish

IPC: H03F3/45

Abstract: A cascode amplifier including an amplifier transistor, a cascode transistor, and a current injection circuit. The amplifier transistor has a first current terminal receiving a first power supply voltage, a second current terminal, and a control terminal receiving an input signal. The cascode transistor has a first current terminal coupled to the second current terminal of the amplifier transistor, a second current terminal coupled to an output terminal; and a control terminal receiving a bias voltage. The current injection circuit has an input receiving the input signal, and first and second outputs coupled to the first and second current terminals of the cascode transistor, respectively. The current injection circuit is configured to present out-of-phase currents to the cascode transistor responsive to the input signal.

公开(公告)号：US10483945B2

公开(公告)日：2019-11-19

申请号：US15852237

申请日：2017-12-22

Applicant: Texas Instruments Incorporated

Inventor： Rajendrakumar Joish ,  Visvesvaraya Pentakota

IPC: H03H11/24 ,  H03H7/25 ,  H01F38/14 ,  H03K17/687 ,  H03G1/00 ,  H04B1/18 ,  H03G3/00 ,  H03G3/30

Abstract: The disclosure provides an RF receiver. The RF receiver includes an input driver. The input driver receives a coarse signal, and generates an input signal. A digital step attenuator (DSA) is coupled to the input driver and receives the input signal. An analog to digital converter (ADC) is coupled to the DSA. The DSA includes a serial capacitor coupled to the input driver. The DSA also includes a sampling capacitor coupled to the ADC.

公开(公告)号：US10340966B2

公开(公告)日：2019-07-02

申请号：US15855052

申请日：2017-12-27

Applicant: Texas Instruments Incorporated

Inventor： Rajendrakumar Joish

IPC: H04B1/16 ,  H03M1/12 ,  H03M1/18

Abstract: The disclosure provides an RF receiver. The RF receiver includes an input driver. The input driver receives a coarse signal, and generates an input signal. A digital step attenuator (DSA) is coupled to the input driver and receives the input signal. An analog to digital converter (ADC) is coupled to the DSA. The DSA includes a sampling capacitor coupled to the ADC. The DSA also includes a time dependent resistor coupled to a source voltage and to the sampling capacitor.