公开(公告)号：US11237223B2

公开(公告)日：2022-02-01

申请号：US16521053

申请日：2019-07-24

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Jo Bito ,  Benjamin Stassen Cook ,  Dok Won Lee ,  Keith Ryan Green ,  Ricky Alan Jackson ,  William David French

IPC: G01R33/00 ,  G01R33/07 ,  B32B15/04 ,  G01D5/14 ,  G01R15/20 ,  G01R33/06 ,  G01R21/08 ,  G01R33/02

Abstract: A structure includes a substrate which includes a surface. The structure also includes a horizontal-type Hall sensor positioned within the substrate and below the surface of the substrate. The structure further includes a patterned magnetic concentrator positioned above the surface of the substrate, and a protective overcoat layer positioned above the magnetic concentrator.

公开(公告)号：US11004929B2

公开(公告)日：2021-05-11

申请号：US16596972

申请日：2019-10-09

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Dok Won Lee ,  Erika Lynn Mazotti ,  Mark Robert Visokay ,  William David French ,  Ricky Alan Jackson ,  Wai Lee

IPC: H01L49/02 ,  G01K7/22 ,  H01L23/522 ,  H01L27/07 ,  G01K7/16

Abstract: Various examples provide an electronic device that includes first and second resistor segments. Each of the resistor segments has a respective doped resistive region formed in a semiconductor substrate. The resistor segments are connected between first and second terminals. The first resistor segment is configured to conduct a current in a first direction, and the second resistor segment is configured to conduct the current in a second different direction. The directions may be orthogonal crystallographic directions of the semiconductor substrate.

公开(公告)号：US10770406B2

公开(公告)日：2020-09-08

申请号：US15820176

申请日：2017-11-21

Applicant: Texas Instruments Incorporated

Inventor： Ricky Alan Jackson ,  Erika Lynn Mazotti ,  Sudtida Lavangkul

IPC: H01L23/00 ,  H01L21/66 ,  H01L21/78 ,  H01L23/58 ,  H01L23/31

Abstract: An example apparatus includes a semiconductor wafer with a plurality of probe pads each formed centered in scribe streets and intersected by saw kerf lanes. Each probe pad includes a plurality of lower level conductor layers arranged in lower level conductor frames, a plurality of lower level vias extending vertically through lower level insulator layers and electrically coupling the lower level conductor frames; a plurality of upper level conductor layers, each forming two portions on two outer edges of the probe pad, the two portions aligned with, spaced from, and on opposite sides of the saw kerf lane, the coverage of the upper level conductor layers being less than about twenty percent; and a plurality of upper level vias extending vertically through upper level insulator layers and coupling the upper level conductor layers electrically to one another and to the lower level conductor layers. Methods are disclosed.

公开(公告)号：US10157861B2

公开(公告)日：2018-12-18

申请号：US15657438

申请日：2017-07-24

Applicant: Texas Instruments Incorporated

Inventor： Ricky Alan Jackson ,  Sudtida Lavangkul ,  Erika Lynn Mazotti

IPC: H01L23/544 ,  H01L23/00 ,  H01L23/528 ,  H01L23/532 ,  H01L23/58 ,  H01L23/31

Abstract: Disclosed embodiments include an integrated circuit having a semiconductor substrate with insulator layers and conductor layers overlying the semiconductor substrate. A scribe region overlying the semiconductor substrate and a periphery of the integrated circuit includes a crack arrest structure and a scribe seal. The crack arrest structure provides first vertical conductor structure that surrounds the periphery of the integrated circuit. The scribe seal is spaced from and surrounded by the crack arrest structure and provides a second vertical conductor structure. The scribe seal includes first and second vias spaced from each other and connected to one of the conductor layers. The first via is a trench via and the second via is a stitch via, with the second via being located closer to the crack arrest structure than the first via.

公开(公告)号：US11782102B2

公开(公告)日：2023-10-10

申请号：US17508706

申请日：2021-10-22

Applicant: Texas Instruments Incorporated

Inventor： Keith Ryan Green ,  Erika Lynn Mazotti ,  William David French ,  Ricky Alan Jackson

IPC: G01R33/07 ,  G01R33/00 ,  H10N52/01 ,  H10N52/80 ,  H10N52/00

CPC classification number: G01R33/072 ,  G01R33/0052 ,  G01R33/077 ,  H10N52/01 ,  H10N52/101 ,  H10N52/80

Abstract: A microelectronic device has a Hall sensor that includes a Hall plate in a semiconductor material. The Hall sensor includes contact regions in the semiconductor material, contacting the Hall plate. The Hall sensor includes an isolation structure with a dielectric material contacting the semiconductor material, on at least two opposite sides of each of the contact regions. The isolation structure is laterally separated from the contact regions by gaps. The Hall sensor further includes a conductive spacer over the gaps, the conductive spacer being separated from the semiconductor material by an insulating layer.

公开(公告)号：US11515266B2

公开(公告)日：2022-11-29

申请号：US17011982

申请日：2020-09-03

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Ricky Alan Jackson ,  Erika Lynn Mazotti ,  Sudtida Lavangkul

IPC: H01L23/544 ,  H01L23/00 ,  H01L21/66 ,  H01L21/78 ,  H01L23/58 ,  H01L23/31

Abstract: An example apparatus includes a semiconductor wafer with a plurality of probe pads each formed centered in scribe streets and intersected by saw kerf lanes. Each probe pad includes a plurality of lower level conductor layers arranged in lower level conductor frames, a plurality of lower level vias extending vertically through lower level insulator layers and electrically coupling the lower level conductor frames; a plurality of upper level conductor layers, each forming two portions on two outer edges of the probe pad, the two portions aligned with, spaced from, and on opposite sides of the saw kerf lane, the coverage of the upper level conductor layers being less than about twenty percent; and a plurality of upper level vias extending vertically through upper level insulator layers and coupling the upper level conductor layers electrically to one another and to the lower level conductor layers. Methods are disclosed.

公开(公告)号：US10705159B2

公开(公告)日：2020-07-07

申请号：US16502317

申请日：2019-07-03

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Erika Lynn Mazotti ,  Dok Won Lee ,  William David French ,  Byron J R Shulver ,  Thomas Dyer Bonifield ,  Ricky Alan Jackson ,  Neil Gibson

IPC: G01R33/04 ,  G01R33/00

Abstract: An integrated fluxgate device has a magnetic core disposed over a semiconductor substrate. A first winding is disposed in a first metallization level above and a second metallization level below the magnetic core, and is configured to generate a first magnetic field in the magnetic core. A second winding is disposed in the first and second metallization levels and is configured to generate a second magnetic field in the magnetic core. A third winding is disposed in the first and second metallization levels and is configured to sense a magnetic field in the magnetic core that is the net of the first and second magnetic fields.

公开(公告)号：US10345397B2

公开(公告)日：2019-07-09

申请号：US15169639

申请日：2016-05-31

Applicant: Texas Instruments Incorporated

Inventor： Erika Lynn Mazotti ,  Dok Won Lee ,  William David French ,  Byron J R Shulver ,  Thomas Dyer Bonifield ,  Ricky Alan Jackson ,  Neil Gibson

IPC: G01R33/04 ,  G01R33/00

Abstract: An integrated fluxgate device has a magnetic core on a control circuit. The magnetic core has a volume and internal structure sufficient to have low magnetic noise and low non-linearity. A stress control structure is disposed proximate to the magnetic core. An excitation winding, a sense winding and a compensation winding are disposed around the magnetic core. An excitation circuit disposed in the control circuit is coupled to the excitation winding, configured to provide current at high frequency to the excitation winding sufficient to generate a saturating magnetic field in the magnetic core during each cycle at the high frequency. An isolation structure is disposed between the magnetic core and the windings, sufficient to enable operation of the excitation winding and the sense winding at the high frequency at low power.

公开(公告)号：US20180090454A1

公开(公告)日：2018-03-29

申请号：US15820176

申请日：2017-11-21

Applicant: Texas Instruments Incorporated

Inventor： Ricky Alan Jackson ,  Erika Lynn Mazotti ,  Sudtida Lavangkul

IPC: H01L23/00 ,  H01L23/544 ,  H01L21/66 ,  H01L21/78 ,  H01L23/31

Abstract: An example apparatus includes a semiconductor wafer with a plurality of probe pads each formed centered in scribe streets and intersected by saw kerf lanes. Each probe pad includes a plurality of lower level conductor layers arranged in lower level conductor frames, a plurality of lower level vias extending vertically through lower level insulator layers and electrically coupling the lower level conductor frames; a plurality of upper level conductor layers, each forming two portions on two outer edges of the probe pad, the two portions aligned with, spaced from, and on opposite sides of the saw kerf lane, the coverage of the upper level conductor layers being less than about twenty percent; and a plurality of upper level vias extending vertically through upper level insulator layers and coupling the upper level conductor layers electrically to one another and to the lower level conductor layers. Methods are disclosed.

公开(公告)号：US09831193B1

公开(公告)日：2017-11-28

申请号：US15169700

申请日：2016-05-31

Applicant: Texas Instruments Incorporated

Inventor： Ricky Alan Jackson ,  Erika Lynn Mazotti ,  Sudtida Lavangkul

IPC: H01L23/528 ,  H01L23/00 ,  H01L23/544 ,  H01L23/31 ,  H01L21/66 ,  H01L21/78

CPC classification number: H01L23/562 ,  H01L21/78 ,  H01L22/32 ,  H01L23/3192 ,  H01L23/585 ,  H01L2223/5446

Abstract: An example apparatus includes a semiconductor wafer with a plurality of probe pads each formed centered in scribe streets and intersected by saw kerf lanes. Each probe pad includes a plurality of lower level conductor layers arranged in lower level conductor frames, a plurality of lower level vias extending vertically through lower level insulator layers and electrically coupling the lower level conductor frames; a plurality of upper level conductor layers, each forming two portions on two outer edges of the probe pad, the two portions aligned with, spaced from, and on opposite sides of the saw kerf lane, the coverage of the upper level conductor layers being less than about twenty percent; and a plurality of upper level vias extending vertically through upper level insulator layers and coupling the upper level conductor layers electrically to one another and to the lower level conductor layers. Methods are disclosed.