公开(公告)号：US07719088B2

公开(公告)日：2010-05-18

申请号：US11254502

申请日：2005-10-20

Applicant: Josef Böck ,  Thomas Meister ,  Reinhard Stengl ,  Herbert Schäfer

Inventor： Josef Böck ,  Thomas Meister ,  Reinhard Stengl ,  Herbert Schäfer

IPC: H01L29/72

CPC classification number: H01L29/66272 ,  H01L29/0821 ,  H01L29/41708 ,  H01L29/732

Abstract: A high-frequency bipolar transistor includes an emitter contact adjoining an emitter connection region, a base contact adjoining a base connection region, and a collector contact adjoining a collector connection region. A first insulation layer is disposed on the base connection region. The collector connection region contains a buried layer, which connects the collector contact to a collector zone. A silicide or salicide region is provided on the buried layer and connects the collector contact to the collector zone in a low-impedance manner. A second insulation layer is disposed on the collector connection region but not on the silicide region.

Abstract translation: 高频双极晶体管包括邻接发射极连接区域的发射极接触件，邻接基极连接区域的基极接触件和邻接集电极连接区域的集电极接触件。 第一绝缘层设置在基底连接区域上。 集电极连接区域包含埋设层，该埋层将集电极触点连接到集电区。 在掩埋层上提供硅化物或自对准硅化物区域，并以低阻抗方式将集电极触点连接到集电极区域。 第二绝缘层设置在集电极连接区域上，但不在硅化物区域上。

公开(公告)号：US07285470B2

公开(公告)日：2007-10-23

申请号：US11240297

申请日：2005-09-30

Applicant: Josef Bock ,  Thomas Meister ,  Reinhard Stengl ,  Herbert Schafer

Inventor： Josef Bock ,  Thomas Meister ,  Reinhard Stengl ,  Herbert Schafer

IPC: H01L21/331

CPC classification number: H01L29/66287 ,  H01L29/0649 ,  H01L29/66242 ,  H01L29/732 ,  H01L29/7378

Abstract: The invention relates to a method for producing a bipolar semiconductor element, especially a bipolar transistor, and a corresponding bipolar semiconductor component. The inventive method comprises the following steps: a first semiconductor area (32, 34) of a first conductivity type (p) is provided above a semiconductor substrate (1); a connecting area (40) of the first conductivity type (p ) is provided above the semiconductor area (32, 34); a first insulating area (35″) is provided above the connecting area (40); a window (F) is formed within the first insulating area (35″) and the connecting area (40) so as to at least partly expose the semiconductor area (32, 34); a sidewall spacer (80) is provided in the window (F) in order to insulate the connecting area (40); a second semiconductor area (60) of the second conductivity type (n+) is provided so as to cover the sidewall spacer (80) and a portion of the surrounding first insulating area (35″); the surrounding first insulating area (35″) and the sidewall spacer (80) are removed in order to form a gap (LS) between the connecting area (40) and the second semiconductor area (60); and the gap (LS) is sealed by means of a second insulating area (100) while a gaseous atmosphere or a vacuum atmosphere is provided inside the sealed gap (LS).

Abstract translation: 本发明涉及一种用于制造双极型半导体元件，特别是双极晶体管的方法和相应的双极半导体元件。 本发明的方法包括以下步骤：第一导电类型（p）的第一半导体区域（32,34）设置在半导体衬底（1）的上方; 在半导体区域（32,34）的上方设置第一导电类型（p +）的连接区域（40）。 第一绝缘区域（35“）设置在连接区域40上方; 在第一绝缘区域（35“）和连接区域（40）内形成窗口（F），以便至少部分地暴露半导体区域（32,34）; 在窗口（F）中设置侧壁间隔件（80）以使连接区域（40）绝缘; 提供第二导电类型（n +）的第二半导体区域（60），以覆盖侧壁间隔物（80）和周围的第一绝缘区域（35“）的一部分; 为了在连接区域（40）和第二半导体区域（60）之间形成间隙（LS），除去周围的第一绝缘区域（35“）和侧壁间隔物（80） 并且在所述密封间隙（LS）的内部设置有气氛或真空气氛的同时，所述间隙（LS）借助于第二绝缘区域（100）密封。

公开(公告)号：US20060040453A1

公开(公告)日：2006-02-23

申请号：US11246420

申请日：2005-10-07

Applicant: Josef Bock ,  Thomas Meister ,  Reinhard Stengl ,  Herbert Schafer

Inventor： Josef Bock ,  Thomas Meister ,  Reinhard Stengl ,  Herbert Schafer

IPC: H01L21/331

CPC classification number: H01L29/66287 ,  H01L29/0821 ,  H01L29/167 ,  H01L29/66242 ,  H01L29/732 ,  H01L29/7378

Abstract: A bipolar transistor comprising a collector region of a first conduction type, and a subcollector region of the first conduction type at a first side of the collector region. The transistor further includes a base region of the second conduction type provided at a second side of the collector region, and an emitter region of the first conduction type which is provided above the base region on the side remote from the collection region. A carbon-doped semiconductor region is provided on the first side alongside the collector region. The bipolar transistor is characterized in that the carbon-doped semiconductor region has a carbon concentration of 1019-1021 cm−3 and the base region has a smaller cross section than the collector region and the collector region has, in the overlap region with the base region, a region having an increased doping compared with the remaining region. The carbon-doped semiconductor region prevents an outdiffusion from the zone of the collector region into the remaining region of the collector region.

Abstract translation: 包括第一导电类型的集电极区域和在集电极区域的第一侧的第一导电类型的子集电极区域的双极晶体管。 晶体管还包括设置在集电极区域的第二侧的第二导电类型的基极区域和设置在远离收集区域的一侧的基极区域上方的第一导电类型的发射极区域。 在集电极区域旁边的第一侧设置碳掺杂半导体区域。 双极晶体管的特征在于，碳掺杂半导体区域的碳浓度为10〜20±0.01cm -3，基极 区域具有比集电极区域更小的横截面，并且在与基极区域的重叠区域中具有与剩余区域相比具有增加的掺杂的区域。 碳掺杂半导体区域防止从集电极区域向集电极区域的剩余区域的扩散。

公开(公告)号：US20060038258A1

公开(公告)日：2006-02-23

申请号：US11254502

申请日：2005-10-20

Applicant: Josef Bock ,  Thomas Meister ,  Reinhard Stengl ,  Hertbert Schafer

Inventor： Josef Bock ,  Thomas Meister ,  Reinhard Stengl ,  Hertbert Schafer

IPC: H01L27/102

CPC classification number: H01L29/66272 ,  H01L29/0821 ,  H01L29/41708 ,  H01L29/732

Abstract: A high-frequency bipolar transistor includes an emitter contact adjoining an emitter connection region, a base contact adjoining a base connection region, and a collector contact adjoining a collector connection region. A first insulation layer is disposed on the base connection region. The collector connection region contains a buried layer, which connects the collector contact to a collector zone. A silicide or salicide region is provided on the buried layer and connects the collector contact to the collector zone in a low-impedance manner. A second insulation layer is disposed on the collector connection region but not on the silicide region.

Abstract translation: 高频双极晶体管包括邻接发射极连接区域的发射极接触件，邻接基极连接区域的基极接触件和邻接集电极连接区域的集电极接触件。 第一绝缘层设置在基底连接区域上。 集电极连接区域包含埋设层，该埋层将集电极触点连接到集电区。 在掩埋层上提供硅化物或自对准硅化物区域，并以低阻抗方式将集电极触点连接到集电极区域。 第二绝缘层设置在集电极连接区域上，但不在硅化物区域上。

公开(公告)号：US5643836A

公开(公告)日：1997-07-01

申请号：US279106

申请日：1994-07-22

Applicant: Thomas Meister ,  Reinhard Stengl

Inventor： Thomas Meister ,  Reinhard Stengl

IPC: H01L21/302 ,  H01L21/304 ,  H01L21/3065 ,  H01L21/3105 ,  H01L21/469 ,  H01L21/768 ,  H01L21/465

CPC classification number: H01L21/76819 ,  H01L21/31055

Abstract: An insulating layer is applied onto the surface of a semiconductor layer structure having elevations up to a maximum step height. The thickness of the insulating layer is greater than the maximum step height. The insulating layer is structured to have irregularities with an essentially identical lateral expanse in the region of the edges of the elevations. The irregularities are planarized by chemical mechanical polishing and/or by deposition, flowing and etch-back of a planarization layer.

Abstract translation: 将绝缘层施加到具有高达最大台阶高度的高度的半导体层结构的表面上。 绝缘层的厚度大于最大台阶高度。 绝缘层被构造成具有在高度边缘的区域中具有基本相同的横向宽度的凹凸。 通过化学机械抛光和/或通过平坦化层的沉积，流动和蚀刻来使不规则性平坦化。

公开(公告)号：US5498567A

公开(公告)日：1996-03-12

申请号：US379861

申请日：1995-04-03

Applicant: Helmut Klose ,  Thomas Meister ,  Hans-Willi Meul ,  Reinhard Stengl

Inventor： Helmut Klose ,  Thomas Meister ,  Hans-Willi Meul ,  Reinhard Stengl

IPC: H01L21/76 ,  H01L21/20 ,  H01L21/331 ,  H01L21/336 ,  H01L29/73 ,  H01L29/732 ,  H01L29/78

CPC classification number: H01L29/66287 ,  H01L21/02381 ,  H01L21/0245 ,  H01L21/02488 ,  H01L21/02505 ,  H01L21/02532 ,  H01L21/02639 ,  H01L29/66651 ,  Y10S148/011

Abstract: A method for the manufacture of a laterally limited single crystal region that is suitable for use as an active part of a transistor, including the steps of: a) providing a substrate made of a single crystal semiconductor material; b) forming a first layer on a surface of the substrate, said first layer being selectively etchable with respect to the substrate; c) forming a second layer on the first layer, the second layer being selectively etchable with respect to the first layer; d) providing an opening in the first and second layers so as to expose an area on the surface of the substrate; e) selectively etching the first layer with respect to the substrate and the second layer so as to provide an undercut between the second layer and the surface of the substrate; f) forming a single crystal region on the exposed surface of the substrate by selective epitaxy: g) doping the second layer such that parts of the second layer adjoining the single-crystal region acting as a channel region form a source region and a drain region; h) producing a gate dielectric at a surface of the single-crystal region; and i) forming a gate electrode that is insulated from the source and drain regions on the gate dielectric.

Abstract translation: 一种用于制造适合用作晶体管的有源部分的横向受限单晶区域的方法，包括以下步骤：a）提供由单晶半导体材料制成的衬底; b）在所述衬底的表面上形成第一层，所述第一层相对于所述衬底可选择性地蚀刻; c）在所述第一层上形成第二层，所述第二层可相对于所述第一层选择性地蚀刻; d）在所述第一层和所述第二层中设置开口以暴露所述基底表面上的区域; e）相对于所述基底和所述第二层选择性地蚀刻所述第一层，以便在所述第二层和所述基底的表面之间提供底切; f）通过选择性外延在衬底的暴露表面上形成单晶区域：g）掺杂第二层，使得与用作沟道区的单晶区相邻的第二层的部分形成源区和漏区 ; h）在单晶区域的表面产生栅电介质; 以及i）形成与栅极电介质上的源极和漏极区域绝缘的栅电极。

公开(公告)号：US5422303A

公开(公告)日：1995-06-06

申请号：US185514

申请日：1994-01-24

Applicant: Helmut Klose ,  Thomas Meister ,  Hans-Willi Meul ,  Reinhard Stengl

Inventor： Helmut Klose ,  Thomas Meister ,  Hans-Willi Meul ,  Reinhard Stengl

IPC: H01L21/76 ,  H01L21/20 ,  H01L21/331 ,  H01L21/336 ,  H01L29/73 ,  H01L29/732 ,  H01L29/78

CPC classification number: H01L29/66287 ,  H01L21/02381 ,  H01L21/0245 ,  H01L21/02488 ,  H01L21/02505 ,  H01L21/02532 ,  H01L21/02639 ,  H01L29/66651 ,  Y10S148/011

Abstract: A method for the manufacture of a laterally limited single crystal region that is suitable for use as an active part of a transistor, including the steps of: a) providing a substrate made of a single crystal semiconductor material; b) forming a first layer on a surface of the substrate, said first layer being selectively etchable with respect to the substrate; c) forming a second layer on the first layer, the second layer being selectively etchable with respect to the first layer; d) providing an opening in the first and second layers so as to expose an area on the surface of the substrate; e) covering surfaces and sidewalls of the second layer with a third layer f) selectively etching the first layer with respect to the substrate and the second layer and the third layer so as to provide an undercut between the second layer and the surface of the substrate; g) forming a single crystal region on the exposed surface of the substrate by selective epitaxy without nucleation occurring at the surface of the third layer; h) forming a collector in the substrate under the single-crystal region; i) forming a base in the single-crystal region; j) doping and configuring the second layer such that it forms a base terminal; and k) forming an emitter above the base.

Abstract translation: 一种用于制造适合用作晶体管的有源部分的横向受限单晶区域的方法，包括以下步骤：a）提供由单晶半导体材料制成的衬底; b）在所述衬底的表面上形成第一层，所述第一层相对于所述衬底可选择性地蚀刻; c）在所述第一层上形成第二层，所述第二层可相对于所述第一层选择性地蚀刻; d）在所述第一层和所述第二层中设置开口以暴露所述基底表面上的区域; e）用第三层覆盖第二层的表面和侧壁f）相对于衬底和第二层和第三层选择性地蚀刻第一层，以便在第二层和衬底的表面之间提供底切 ; g）通过选择性外延在第三层的表面上没有成核而在衬底的暴露表面上形成单晶区; h）在单晶区域下在衬底中形成集电体; i）在单晶区域形成碱; j）掺杂和配置第二层，使得它形成基极; 和k）在基底上形成发射体。

公开(公告)号：US20100155896A1

公开(公告)日：2010-06-24

申请号：US12716692

申请日：2010-03-03

Applicant: Josef Böck ,  Thomas Meister ,  Reinhard Stengl ,  Herbert Schafer

Inventor： Josef Böck ,  Thomas Meister ,  Reinhard Stengl ,  Herbert Schafer

IPC: H01L29/73

CPC classification number: H01L29/66272 ,  H01L29/0821 ,  H01L29/41708 ,  H01L29/732

Abstract: A high-frequency bipolar transistor includes an emitter contact adjoining an emitter connection region, a base contact adjoining a base connection region, and a collector contact adjoining a collector connection region. A first insulation layer is disposed on the base connection region. The collector connection region contains a buried layer, which connects the collector contact to a collector zone. A silicide or salicide region is provided on the buried layer and connects the collector contact to the collector zone in a low-impedance manner. A second insulation layer is disposed on the collector connection region but not on the silicide region.

Abstract translation: 高频双极晶体管包括邻接发射极连接区域的发射极接触件，邻接基极连接区域的基极接触件和邻接集电极连接区域的集电极接触件。 第一绝缘层设置在基底连接区域上。 集电极连接区域包含埋设层，该埋层将集电极触点连接到集电区。 在掩埋层上提供硅化物或自对准硅化物区域，并以低阻抗方式将集电极触点连接到集电极区域。 第二绝缘层设置在集电极连接区域上，但不在硅化物区域上。

公开(公告)号：US07371650B2

公开(公告)日：2008-05-13

申请号：US10532894

申请日：2003-10-24

Applicant: Josef Böck ,  Rudolf Lachner ,  Thomas Meister ,  Reinhard Stengl ,  Herbert Schäfer ,  Martin Seck

Inventor： Josef Böck ,  Rudolf Lachner ,  Thomas Meister ,  Reinhard Stengl ,  Herbert Schäfer ,  Martin Seck

IPC: H01L21/331

CPC classification number: H01L29/66272 ,  H01L21/8222 ,  H01L27/0825 ,  H01L29/0821

Abstract: A method for fabricating a transistor structure with a first and a second bipolar transistor having different collector widths is presented. The method includes providing a semiconductor substrate, introducing a first buried layer of the first bipolar transistor and a second buried layer of the second bipolar transistor into the semiconductor substrate, and producing at least a first collector region having a first collector width on the first buried layer and a second collector region having a second collector width on the second buried layer. A first collector zone having a first thickness is produced on the second buried layer for production of the second collector width. A second collector zone having a second thickness is produced on the first collector zone. At least one insulation region is produced that isolates at least the collector regions from one another.

Abstract translation: 提出了一种制造具有不同集电极宽度的第一和第二双极晶体管的晶体管结构的方法。 该方法包括提供半导体衬底，将第一双极晶体管的第一掩埋层和第二双极晶体管的第二掩埋层引入到半导体衬底中，并且至少在第一掩埋层上产生具有第一集电极宽度的第一集电极区域 层和在第二掩埋层上具有第二集电极宽度的第二集电极区。 在第二掩埋层上产生具有第一厚度的第一收集器区，用于产生第二收集器宽度。 在第一收集器区域上产生具有第二厚度的第二收集器区域。 产生至少一个绝缘区域，其至少隔离收集器区域彼此。

公开(公告)号：US07135757B2

公开(公告)日：2006-11-14

申请号：US10912344

申请日：2004-08-04

Applicant: Reinhard Stengl ,  Thomas Meister ,  Herbert Schäfer ,  Martin Franosch

Inventor： Reinhard Stengl ,  Thomas Meister ,  Herbert Schäfer ,  Martin Franosch

IPC: H01L27/082

CPC classification number: H01L29/66287 ,  H01L29/7322

Abstract: A bipolar transistor includes a first layer with a collector. A second layer has a base cutout for a base. A third layer includes a lead for the base. The third layer is formed with an emitter cutout for an emitter. An undercut is formed in the second layer adjoining the base cutout. The base is at least partially located in the undercut. In order to obtain a low transition resistance between the lead and the base, an intermediate layer is provided between the first and the second layer. The intermediate layer is selectively etchable with respect to the second layer. At least in the region of the undercut between the lead and the base, a base connection zone is provided that can be adjusted independent of other production conditions. The intermediate layer is removed in a contact region with the base.

Abstract translation: 双极晶体管包括具有集电极的第一层。 第二层具有用于基座的基部切口。 第三层包括用于底座的引线。 第三层形成有用于发射极的发射极切口。 在与基座切口相邻的第二层中形成底切。 基部至少部分位于底切中。 为了在引线和基底之间获得低的过渡电阻，在第一和第二层之间设置中间层。 中间层相对于第二层可选择性地蚀刻。 至少在引线和基座之间的底切区域中，提供可以独立于其他生产条件进行调节的基础连接区域。 在与基底的接触区域中去除中间层。