Process for producing lateral bipolar transistor
    1.
    发明授权
    Process for producing lateral bipolar transistor 失效
    制造横向双极晶体管的工艺

    公开(公告)号:US5714397A

    公开(公告)日:1998-02-03

    申请号:US666101

    申请日:1996-06-19

    申请人: Helmut Klose

    发明人: Helmut Klose

    CPC分类号: H01L29/66265 H01L29/7317

    摘要: In a lateral bipolar transistor and a method for producing the same, an emitter layer and a collector layer are disposed on a structured dielectric layer. The structured dielectric layer is located in a plane of a base layer and is interrupted by the base layer in such a way that between the base layer and portions of the structured dielectric layer, the base layer is contacted on one side by the emitter layer and on the opposite side by the collector layer.

    摘要翻译: 在横向双极晶体管及其制造方法中,发射极层和集电极层设置在结构化电介质层上。 结构化介电层位于基底层的平面中,并被基底层间隔开,使得在基底层和结构化介电层的部分之间,基底层在一侧被发射极层接触,并且 在集电体层的相对侧。

    Acceleration sensor and method for manufacturing same
    2.
    发明授权
    Acceleration sensor and method for manufacturing same 失效
    加速度传感器及其制造方法

    公开(公告)号:US5447067A

    公开(公告)日:1995-09-05

    申请号:US207080

    申请日:1994-03-08

    摘要: An acceleration sensor has a proof mass attached by resilient elements, in the form of micromechanical components, in a monocrystalline silicon layer of an SOI (silicon-on-insulator) substrate, the insulator layer of the substrate being removed under the structure which is susceptible to acceleration, in order to enable free mobility of the micromechanical components. Piezoresistors are provided for detecting movement of the proof mass, the piezoresistors supplying electrical signals to an evaluation circuit.

    摘要翻译: 加速度传感器具有通过在MEMS(绝缘体上硅)衬底的单晶硅层中以微机械部件的形式的弹性元件附着的校验物质,该衬底的绝缘体层在易感的结构下被去除 以加速,以便实现微机械部件的自由移动。 提供压阻器用于检测检测质量块的运动,压电电阻器将电信号提供给评估电路。

    Tunnel effect acceleration sensor
    3.
    发明授权
    Tunnel effect acceleration sensor 失效
    隧道效应加速度传感器

    公开(公告)号:US5431051A

    公开(公告)日:1995-07-11

    申请号:US219538

    申请日:1994-03-29

    IPC分类号: G01P15/08 H01L29/88 G01P15/13

    CPC分类号: G01P15/0894

    摘要: An acceleration sensor is produced on a silicon substrate by etching to leave a cantilevered beam of polysilicon with a tip on the substrate projecting toward this beam. Acceleration of the sensor causes the beam to bend, thereby changing the spacing between the tip and the beam, and thereby also changing the tunnel current, which is measured. Electrodes are provided that, given application of a potential thereto, effect an electrostatic compensation of the bending of the beam.

    摘要翻译: 通过蚀刻在硅衬底上产生加速度传感器,以留下多晶硅的悬臂梁,衬底上的尖端朝向该梁突出。 传感器的加速度导致光束弯曲,从而改变尖端和光束之间的间距,从而也改变测量的隧道电流。 提供电极,其给予施加电位以对光束的弯曲进行静电补偿。

    Method for manufacturing a bipolar transistor in a substrate
    4.
    发明授权
    Method for manufacturing a bipolar transistor in a substrate 失效
    在基板中制造双极晶体管的方法

    公开(公告)号:US5358882A

    公开(公告)日:1994-10-25

    申请号:US030901

    申请日:1993-03-15

    摘要: A method for producing a bipolar transistor completely surrounded by an insulating trench in a substrate. Insulating regions at the surface of the substrate can be produced by depositing an SiO.sub.2 layer on the basis of thermal decomposition of TEOS and subsequent structuring of the SiO.sub.2 layer. The insulating regions can be employed as a self-aligning mask for the production of a collector terminal and of a substrate terminal.

    摘要翻译: 一种完全由基板中的绝缘沟槽围绕的双极晶体管的制造方法。 可以通过在TEOS的热分解和SiO 2层的结构化的基础上沉积SiO 2层来制造衬底表面的绝缘区域。 绝缘区域可以用作用于生产集电极端子和衬底端子的自对准掩模。

    DRAM cell arrangement and method for the manufacture thereof
    7.
    发明授权
    DRAM cell arrangement and method for the manufacture thereof 有权
    DRAM单元布置及其制造方法

    公开(公告)号:US06172391B2

    公开(公告)日:2001-01-09

    申请号:US09140972

    申请日:1998-08-27

    IPC分类号: H01L2978

    摘要: An element that prevents the formation of a channel is arranged in a level of the channel region (Kaa) at one of two opposite sidewalls of a semiconductor structure that has a source/drain region (S/D1a) and a channel region (Kaa) of a vertical selection transistor arranged therebelow. The source/drain region as well as a respective word line (W1a) adjoin at both sidewalls. For folded bit lines (B1a), respectively two word lines (W1a) can be formed in the trenches (G2a). The elements of semiconductor structures neighboring along one of the trenches (G2a) are then arranged in alternation at a sidewall of the trench (G2a) and at a sidewall of a neighboring trench (D2a). A storage capacitor can be arranged over a substrate (1a) or can be buried in the substrate (1a). The connection of the selection transistor to a bit line (B1a) can ensue in many ways.

    摘要翻译: 防止形成通道的元件被布置在具有源极/漏极区域(S / D1a)和沟道区域(Kaa))的半导体结构的两个相对侧壁之一处的沟道区域(Kaa)的水平面中, 的垂直选择晶体管。 源极/漏极区域以及相应的字线(W1a)在两个侧壁处相邻。 对于折叠位线(B1a),可以在沟槽(G2a)中分别形成两个字线(W1a)。 然后沿沟槽(G2a)之一相邻的半导体结构的元件交替地布置在沟槽(G2a)的侧壁和相邻沟槽(D2a)的侧壁处。 存储电容器可以布置在基板(1a)上方或者可以被埋在基板(1a)中。 选择晶体管与位线(B1a)的连接可以以许多方式进行。

    Read-only memory cell configuration with trench MOS transistor and
widened drain region
    8.
    发明授权
    Read-only memory cell configuration with trench MOS transistor and widened drain region 失效
    具有沟槽MOS晶体管的只读存储单元配置和扩大的漏极区域

    公开(公告)号:US6043543A

    公开(公告)日:2000-03-28

    申请号:US86011

    申请日:1998-05-28

    申请人: Helmut Klose

    发明人: Helmut Klose

    CPC分类号: H01L27/11273 H01L27/112

    摘要: A read-only memory cell configuration and a method for its production include a substrate formed of semiconductor material having memory cells disposed in a cell field in a region of a main area. Each memory cell has at least one MOS transistor with a source region, a drain region, a channel region, a gate dielectric and a gate electrode. The drain region is connected to a bit line and the gate electrode is connected to a word line. The MOS transistor is formed by a trench starting at the main area and reaching as far as the source region. Side walls of the trench are disposed at an angle of approximately 45.degree. to approximately 80.degree. relative to the main area and are doped with a doping material of a predetermined conductivity for defining the programming of the MOS transistor.

    摘要翻译: 只读存储单元结构及其制造方法包括由半导体材料形成的衬底,其具有设置在主区域的区域中的单元区域中的存储单元。 每个存储单元具有至少一个具有源极区,漏极区,沟道区,栅极电介质和栅电极的MOS晶体管。 漏极区域连接到位线,栅电极连接到字线。 MOS晶体管由在主区域开始并到达源极区域的沟槽形成。 沟槽的侧壁相对于主区域以大约45度至大约80度的角度设置,并且掺杂有预定电导率的掺杂材料以限定MOS晶体管的编程。

    Semiconductor component for vertical integration and manufacturing method
    9.
    发明授权
    Semiconductor component for vertical integration and manufacturing method 失效
    半导体元件垂直整合制造方法

    公开(公告)号:US5930596A

    公开(公告)日:1999-07-27

    申请号:US721980

    申请日:1996-09-27

    摘要: A terminal metallization (8) is applied onto and structured on a layer structure on the upper side of the component, the terminal metallization is applied on the upper side of an insulating layer (7) with an opening on a metallization (6) provided for electrical connection. By filling a hole produced in a covering dielectric with metal, a contact rod (12) seated on this terminal metallization (8) is formed. This contact rod is resiliently movable in a surrounding opening (14) of the component on the free part of the terminal metallization (8) anchored in the layer structure. This enables the reversible contacting of the component to a further component arranged vertically thereto, whereby the planar upper sides lying opposite one another can be brought into intimate contact because the contact rod (12) pressed against a contact (15) of the other component is pressed back into the opening (14) and an adequately firm connection of the contacts is achieved by the spring power of the terminal metallization (8).

    摘要翻译: PCT No.PCT / DE95 / 00313 Sec。 371日期1996年9月27日第 102(e)1996年9月27日PCT 1995年3月7日PCT PCT。 公开号WO96 / 26568 PCT 日期1995年10月5日端子金属化(8)被施加到构件的上侧上的层结构上并在其上构造,端子金属化被施加在绝缘层(7)的上侧,金属化开口 (6)用于电连接。 通过用金属填充在覆盖电介质中产生的孔,形成了位于该端子金属化(8)上的接触棒(12)。 该接触杆可以在锚定在层结构中的端子金属化(8)的自由部分上的部件的周围开口(14)中弹性移动。 这使得部件与其垂直方向布置的另一部件可逆地接触,由此,压接在另一部件的接触件(15)上的接触杆(12)是彼此相对的平面上侧面 压入到开口(14)中,通过端子金属化(8)的弹簧功率实现触点的充分牢固的连接。

    Method for manufacturing an acceleration sensor
    10.
    发明授权
    Method for manufacturing an acceleration sensor 失效
    加速度传感器的制造方法

    公开(公告)号:US5700702A

    公开(公告)日:1997-12-23

    申请号:US676282

    申请日:1996-07-17

    摘要: Manufacturing method for an acceleration sensor on silicon, whereby, following the manufacture of the doped regions required for the electronic function elements, a polysilicon layer is deposited. The polysilicon layer is structured such that a portion of this polysilicon layer forms an electrode (for example, the emitter electrode (9) and the collector electrode (10) of a transistor) and a sensor layer (17) provided as sensor element.

    摘要翻译: PCT No.PCT / DE95 / 00022 Sec。 371日期:1996年7月17日 102(e)日期1996年7月17日PCT 1995年1月10日PCT PCT。 第WO95 / 19572号公报 日期1995年7月20日硅上的加速度传感器的制造方法,其中,在制造电子功能元件所需的掺杂区域之后,沉积多晶硅层。 多晶硅层被构造为使得该多晶硅层的一部分形成电极(例如,发射极(9)和晶体管的集电极(10))和设置为传感器元件的传感器层(17)。