利索-全球专利检索

  1. 登录
  2. 注册

搜索结果

30 条记录 (耗时 0.03 秒)

    Packaging substrate having pattern-matched metal layers
    13.
    发明授权
    Packaging substrate having pattern-matched metal layers 失效
    具有图案匹配金属层的包装基板

    公开(公告)号：US07759787B2

    公开(公告)日：2010-07-20

    申请号：US11935834

    申请日：2007-11-06

    申请人： Sri M. Sri-Jayantha ,  Hien P. Dang ,  Vijayeshwar D. Khanna ,  Arun Sharma

    发明人： Sri M. Sri-Jayantha ,  Hien P. Dang ,  Vijayeshwar D. Khanna ,  Arun Sharma

    IPC分类号： H01L23/053 ,  H01L23/12

    CPC分类号： H05K1/0271 ,  H01L23/49833 ,  H01L23/49838 ,  H01L2924/0002 ,  H05K3/0005 ,  H05K3/4644 ,  H05K2201/09136 ,  H05K2201/09227 ,  H05K2203/1572 ,  Y10T29/49004 ,  Y10T29/49155 ,  H01L2924/00

    摘要： A pattern matched pair of a front metal interconnect layer and a back metal interconnect layer having matched thermal expansion coefficients are provided for a reduced warp packaging substrate. Metal interconnect layers containing a high density of wiring and complex patterns are first developed so that interconnect structures for signal transmission are optimized for electrical performance. Metal interconnect layers containing a low density wiring and relatively simple patterns are then modified to match the pattern of a mirror image metal interconnect layer located on the opposite side of the core and the same number of metal interconnect layer away from the core. During this pattern-matching process, the contiguity of electrical connection in the metal layers with a low density wiring may become disrupted. The disruption is healed by an additional design step in which the contiguity of the electrical connection in the low density is reestablished.

    摘要翻译： 提供具有匹配的热膨胀系数的前金属互连层和背金属互连层的图案匹配对，用于经缩短的经向包装基板。 首先开发了包含高密度布线和复杂图案的金属互连层，使得用于信号传输的互连结构被优化用于电性能。 然后修改包含低密度布线和相对简单图案的金属互连层，以匹配位于芯的相对侧上的镜像金属互连层的图案和与芯相距相同数量的金属互连层。 在这种模式匹配过程中，具有低密度布线的金属层中的电连接的连续性可能会被破坏。 通过额外的设计步骤来治愈中断，其中重新建立低密度电连接的邻接性。

    PACKAGING SUBSTRATE HAVING PATTERN-MATCHED METAL LAYERS
    14.
    发明申请
    PACKAGING SUBSTRATE HAVING PATTERN-MATCHED METAL LAYERS 失效
    包装与图案匹配的金属层的衬底

    公开(公告)号：US20090114429A1

    公开(公告)日：2009-05-07

    申请号：US11935834

    申请日：2007-11-06

    申请人： Sri M. Sri-Jayantha ,  Hien P. Dang ,  Vijayeshwar D. Khanna ,  Arun Sharma

    发明人： Sri M. Sri-Jayantha ,  Hien P. Dang ,  Vijayeshwar D. Khanna ,  Arun Sharma

    IPC分类号： H05K1/03 ,  G06F17/50 ,  H05K3/00

    CPC分类号： H05K1/0271 ,  H01L23/49833 ,  H01L23/49838 ,  H01L2924/0002 ,  H05K3/0005 ,  H05K3/4644 ,  H05K2201/09136 ,  H05K2201/09227 ,  H05K2203/1572 ,  Y10T29/49004 ,  Y10T29/49155 ,  H01L2924/00

    摘要： A pattern matched pair of a front metal interconnect layer and a back metal interconnect layer having matched thermal expansion coefficients are provided for a reduced warp packaging substrate. Metal interconnect layers containing a high density of wiring and complex patterns are first developed so that interconnect structures for signal transmission are optimized for electrical performance. Metal interconnect layers containing a low density wiring and relatively simple patterns are then modified to match the pattern of a mirror image metal interconnect layer located on the opposite side of the core and the same number of metal interconnect layer away from the core. During this pattern-matching process, the contiguity of electrical connection in the metal layers with a low density wiring may become disrupted. The disruption is healed by an additional design step in which the contiguity of the electrical connection in the low density is reestablished.

    摘要翻译： 提供具有匹配的热膨胀系数的前金属互连层和背金属互连层的图案匹配对，用于经缩短的经向包装基板。 首先开发了包含高密度布线和复杂图案的金属互连层，使得用于信号传输的互连结构被优化用于电性能。 然后修改包含低密度布线和相对简单图案的金属互连层，以匹配位于芯的相对侧上的镜像金属互连层的图案和与芯相距相同数量的金属互连层。 在这种模式匹配过程中，具有低密度布线的金属层中的电连接的连续性可能会被破坏。 通过额外的设计步骤来治愈中断，其中重新建立低密度电连接的邻接性。

    Method and system for real-time estimation and prediction of the thermal state of a microprocessor unit
    17.
    发明授权
    Method and system for real-time estimation and prediction of the thermal state of a microprocessor unit 失效
    用于实时估计和预测微处理器单元的热状态的方法和系统

    公开(公告)号：US07695188B2

    公开(公告)日：2010-04-13

    申请号：US12021242

    申请日：2008-01-28

    申请人： Sri M. Sri-Jayantha ,  Hien P. Dang ,  Arun Sharma

    发明人： Sri M. Sri-Jayantha ,  Hien P. Dang ,  Arun Sharma

    IPC分类号： G01K7/00 ,  G01K3/00 ,  G01J5/00

    CPC分类号： G06F1/206

    摘要： An apparatus for predicting a thermal state of a system including a semiconductor chip includes a plurality of sensors formed on the semiconductor chip for measuring a temperature at first locations of the semiconductor chip, a model developer for developing a model for estimating a temperature at second locations of the semiconductor chip which are other than the first locations, a mapping unit for mapping an instruction cache associated with the chip into a sequence of X-Y distributed quanta of heat packets, and a predicting unit for predicting a future temperature of the chip based on an execution of an instruction stream in the instruction cache.

    摘要翻译： 一种用于预测包括半导体芯片的系统的热状态的装置包括形成在半导体芯片上的用于测量半导体芯片的第一位置处的温度的多个传感器，用于开发用于估计第二位置处的温度的模型的模型显影器 所述半导体芯片不同于所述第一位置，映射单元，用于将与所述芯片相关联的指令高速缓存到热分组的XY分布量子序列中;以及预测单元，用于基于所述芯片的未来温度预测 执行指令缓存中的指令流。

    PACKAGING SUBSTRATE HAVING PATTERN-MATCHED METAL LAYERS
    20.
    发明申请
    PACKAGING SUBSTRATE HAVING PATTERN-MATCHED METAL LAYERS 有权
    包装与图案匹配的金属层的衬底

    公开(公告)号：US20100218364A1

    公开(公告)日：2010-09-02

    申请号：US12775970

    申请日：2010-05-07

    申请人： Sri M. Sri-Jayantha ,  Hien P. Dang ,  Vijayeshwar D. Khanna ,  Arun Sharma

    发明人： Sri M. Sri-Jayantha ,  Hien P. Dang ,  Vijayeshwar D. Khanna ,  Arun Sharma

    IPC分类号： H05K3/22

    CPC分类号： H05K1/0271 ,  H01L23/49833 ,  H01L23/49838 ,  H01L2924/0002 ,  H05K3/0005 ,  H05K3/4644 ,  H05K2201/09136 ,  H05K2201/09227 ,  H05K2203/1572 ,  Y10T29/49004 ,  Y10T29/49155 ,  H01L2924/00

    摘要： A pattern matched pair of a front metal interconnect layer and a back metal interconnect layer having matched thermal expansion coefficients are provided for a reduced warp packaging substrate. Metal interconnect layers containing a high density of wiring and complex patterns are first developed so that interconnect structures for signal transmission are optimized for electrical performance. Metal interconnect layers containing a low density wiring and relatively simple patterns are then modified to match the pattern of a mirror image metal interconnect layer located on the opposite side of the core and the same number of metal interconnect layer away from the core. During this pattern-matching process, the contiguity of electrical connection in the metal layers with a low density wiring may become disrupted. The disruption is healed by an additional design step in which the contiguity of the electrical connection in the low density is reestablished.

    摘要翻译： 提供具有匹配的热膨胀系数的前金属互连层和背金属互连层的图案匹配对，用于经缩短的经向包装基板。 首先开发了包含高密度布线和复杂图案的金属互连层，使得用于信号传输的互连结构被优化用于电性能。 然后修改包含低密度布线和相对简单图案的金属互连层，以匹配位于芯的相对侧上的镜像金属互连层的图案和与芯相距相同数量的金属互连层。 在这种模式匹配过程中，具有低密度布线的金属层中的电连接的连续性可能会被破坏。 通过额外的设计步骤来治愈中断，其中重新建立低密度电连接的邻接性。