公开(公告)号：US20070138573A1

公开(公告)日：2007-06-21

申请号：US11565913

申请日：2006-12-01

申请人： Keiichiro KASHIHARA ,  Tomonori Okudaira ,  Tadashi Yamaguchi ,  Atsushi Ishinaga ,  Kenshi Kanegae ,  Akihiko Tsuzumitani

发明人： Keiichiro KASHIHARA ,  Tomonori Okudaira ,  Tadashi Yamaguchi ,  Atsushi Ishinaga ,  Kenshi Kanegae ,  Akihiko Tsuzumitani

IPC分类号： H01L29/76 ,  H01L21/336

CPC分类号： H01L29/665 ,  H01L29/6653 ,  H01L29/6656 ,  H01L29/6659 ,  H01L29/7833

摘要： A semiconductor device according to the present invention comprises a silicon substrate, a gate electrode formed on a main surface of the silicon substrate with a gate insulation film therethrough, a sidewall spacer formed so as to cover a side surface of the gate electrode and including at least two layers of a silicon oxide film as a lowermost layer and a silicon nitride film formed thereon, a source region and a drain region formed in the main surface of the silicon substrate so as to sandwich the gate electrode, a protection film formed so as to cover an end surface of the silicon oxide film without extending below said silicon nitride film, the end surface being on a side of said source region and said drain region, and a metal silicide layer formed in the source region and the drain region on a side of said protection film away from said gate electrode.

摘要翻译： 根据本发明的半导体器件包括硅衬底，在硅衬底的主表面上形成有栅绝缘膜的栅电极，形成为覆盖栅电极的侧表面的侧壁间隔件， 至少两层作为最下层的氧化硅膜和形成在其上的氮化硅膜，在硅衬底的主表面中形成的源极区和漏极区，以便夹着栅电极，保护膜形成为 为了覆盖氧化硅膜的端面而不延伸到所述氮化硅膜的下方，所述端面位于所述源极区域和所述漏极区域的一侧，以及形成在所述源极区域和所述漏极区域中的金属硅化物层 所述保护膜的一侧远离所述栅电极。

公开(公告)号：US5668041A

公开(公告)日：1997-09-16

申请号：US632194

申请日：1996-04-15

申请人： Tomonori Okudaira ,  Takeharu Kuroiwa ,  Nobuo Fujiwara ,  Keiichiro Kashihara

发明人： Tomonori Okudaira ,  Takeharu Kuroiwa ,  Nobuo Fujiwara ,  Keiichiro Kashihara

IPC分类号： H01L21/28 ,  H01L21/02 ,  H01L21/3205 ,  H01L21/768 ,  H01L21/822 ,  H01L21/8242 ,  H01L21/8246 ,  H01L23/522 ,  H01L27/04 ,  H01L27/105 ,  H01L21/70 ,  H01L27/00

CPC分类号： H01L27/10852 ,  H01L21/3205 ,  H01L28/40 ,  H01L28/55 ,  Y10S257/915 ,  Y10S438/978

摘要： According to a semiconductor device and a method of manufacturing thereof, a sidewall spacer is formed at a sidewall of a contact hole, in a recess portion defined by the sidewall of the contact hole and a buried conductive layer, having a film thickness gradually increasing from a top face corner of an interlayer insulation film to the surface of the buried conductive layer. Therefore, a semiconductor device that can achieve favorable breakdown voltage and anti-leak characteristics between a lower electrode layer and an upper electrode layer forming a capacitor of a DRAM.

摘要翻译： 根据半导体器件及其制造方法，在由接触孔的侧壁限定的凹部和埋入导电层的接触孔的侧壁处形成侧壁间隔物，其中膜厚度从 层间绝缘膜的顶面角到掩埋导电层的表面。 因此，可以在形成DRAM的电容器的下电极层和上电极层之间实现良好的击穿电压和防漏电特性的半导体装置。

公开(公告)号：US5652186A

公开(公告)日：1997-07-29

申请号：US632195

申请日：1996-04-15

申请人： Tomonori Okudaira ,  Takeharu Kuroiwa ,  Nobuo Fujiwara ,  Keiichiro Kashihara

发明人： Tomonori Okudaira ,  Takeharu Kuroiwa ,  Nobuo Fujiwara ,  Keiichiro Kashihara

IPC分类号： H01L21/28 ,  H01L21/02 ,  H01L21/3205 ,  H01L21/768 ,  H01L21/822 ,  H01L21/8242 ,  H01L21/8246 ,  H01L23/522 ,  H01L27/04 ,  H01L27/105 ,  H01L21/00

CPC分类号： H01L27/10852 ,  H01L21/3205 ,  H01L28/40 ,  H01L28/55 ,  Y10S257/915 ,  Y10S438/978

摘要： According to a semiconductor device and a method of manufacturing thereof, a sidewall spacer is formed at a sidewall of a contact hole, in a recess portion defined by the sidewall of the contact hole and a buried conductive layer, having a film thickness gradually increasing from a top face corner of an interlayer insulation film to the surface of the buried conductive layer. Therefore, a semiconductor device that can achieve favorable breakdown voltage and anti-leak characteristics between a lower electrode layer and an upper electrode layer forming a capacitor of a DRAM.

摘要翻译： 根据半导体器件及其制造方法，在由接触孔的侧壁限定的凹部和埋入导电层的接触孔的侧壁处形成侧壁间隔物，其中膜厚度从 层间绝缘膜的顶面角到掩埋导电层的表面。 因此，可以在形成DRAM的电容器的下电极层和上电极层之间实现良好的击穿电压和防漏电特性的半导体装置。

公开(公告)号：US20110207317A1

公开(公告)日：2011-08-25

申请号：US13053733

申请日：2011-03-22

申请人： Toshiaki Tsutsumi ,  Tomonori Okudaira ,  Keiichiro Kashihara ,  Tadashi Yamaguchi

发明人： Toshiaki Tsutsumi ,  Tomonori Okudaira ,  Keiichiro Kashihara ,  Tadashi Yamaguchi

IPC分类号： H01L21/768

CPC分类号： H01L23/485 ,  H01L21/28518 ,  H01L2924/0002 ,  H01L2924/00

摘要： There is provided a semiconductor device having a metal silicide layer which can suppress the malfunction and the increase in power consumption of the device. The semiconductor device has a semiconductor substrate containing silicon and having a main surface, first and second impurity diffusion layers formed in the main surface of the semiconductor substrate, a metal silicide formed over the second impurity diffusion layer, and a silicon nitride film and a first interlayer insulation film sequentially stacked over the metal silicide. In the semiconductor device, a contact hole penetrating through the silicon nitride film and the first interlayer insulation film, and reaching the surface of the metal silicide is formed. The thickness of a portion of the metal silicide situated immediately under the contact hole is smaller than the thickness of a portion of the metal silicide situated around the contact hole.

摘要翻译： 提供了具有金属硅化物层的半导体器件，其可以抑制器件的故障和功率消耗的增加。 半导体器件具有包含硅并具有主表面的半导体衬底，形成在半导体衬底的主表面中的第一和第二杂质扩散层，形成在第二杂质扩散层上的金属硅化物，以及氮化硅膜和第一 层间绝缘膜依次层叠在金属硅化物上。 在半导体器件中，形成穿过氮化硅膜和第一层间绝缘膜并到达金属硅化物表面的接触孔。 位于接触孔正下方的金属硅化物的一部分的厚度小于位于接触孔周围的金属硅化物的一部分的厚度。

公开(公告)号：US07872314B2

公开(公告)日：2011-01-18

申请号：US12727334

申请日：2010-03-19

申请人： Tadashi Yamaguchi ,  Keiichiro Kashihara ,  Tomonori Okudaira ,  Toshiaki Tsutsumi

发明人： Tadashi Yamaguchi ,  Keiichiro Kashihara ,  Tomonori Okudaira ,  Toshiaki Tsutsumi

IPC分类号： H01L23/62

CPC分类号： H01L21/823814 ,  H01L21/26506 ,  H01L21/823835 ,  H01L21/823864 ,  H01L29/665 ,  H01L29/6653 ,  H01L29/6656 ,  H01L29/6659 ,  H01L29/7833

摘要： An N-type source region and an N-type drain region of N-channel type MISFETs are implanted with ions (containing at least one of F, Si, C, Ge, Ne, Ar and Kr) with P-channel type MISFETs being covered by a mask layer. Then, each gate electrode, source region and drain region of the N- and P-channel type MISFETs are subjected to silicidation (containing at least one of Ni, Ti, Co, Pd, Pt and Er). This can suppress a drain-to-body off-leakage current (substrate leakage current) in the N-channel type MISFETs without degrading the drain-to-body off-leakage current in the P-channel type MISFETs.

摘要翻译： 离子（含有F，Si，C，Ge，Ne，Ar和Kr中的至少一个）注入N沟道型MISFET的N型源极区域和N型漏极区域，P沟道型MISFET为 被掩模层覆盖。 然后，对N沟道型MISFET和P沟道型MISFET的各栅电极，源极区和漏极区进行硅化（含有Ni，Ti，Co，Pd，Pt和Er中的至少一种）。 这可以抑制N沟道型MISFET中的漏 - 漏泄漏电流（衬底泄漏电流），而不会降低P沟道型MISFET中的漏 - 漏泄漏电流。

公开(公告)号：US07696050B2

公开(公告)日：2010-04-13

申请号：US11537208

申请日：2006-09-29

申请人： Tadashi Yamaguchi ,  Keiichiro Kashihara ,  Tomonori Okudaira ,  Toshiaki Tsutsumi

发明人： Tadashi Yamaguchi ,  Keiichiro Kashihara ,  Tomonori Okudaira ,  Toshiaki Tsutsumi

IPC分类号： H01L21/336

CPC分类号： H01L21/823814 ,  H01L21/26506 ,  H01L21/823835 ,  H01L21/823864 ,  H01L29/665 ,  H01L29/6653 ,  H01L29/6656 ,  H01L29/6659 ,  H01L29/7833

摘要： An N-type source region and an N-type drain region of N-channel type MISFETs are implanted with ions (containing at least one of F, Si, C, Ge, Ne, Ar and Kr) with P-channel type MISFETs being covered by a mask layer. Then, each gate electrode, source region and drain region of the N- and P-channel type MISFETs are subjected to silicidation (containing at least one of Ni, Ti, Co, Pd, Pt and Er). This can suppress a drain-to-body off-leakage current (substrate leakage current) in the N-channel type MISFETs without degrading the drain-to-body off-leakage current in the P-channel type MISFETs.

摘要翻译： 离子（含有F，Si，C，Ge，Ne，Ar和Kr中的至少一个）注入N沟道型MISFET的N型源极区域和N型漏极区域，P沟道型MISFET为 被掩模层覆盖。 然后，对N沟道型MISFET和P沟道型MISFET的各栅电极，源极区和漏极区进行硅化（含有Ni，Ti，Co，Pd，Pt和Er中的至少一种）。 这可以抑制N沟道型MISFET中的漏 - 漏泄漏电流（衬底泄漏电流），而不会降低P沟道型MISFET中的漏 - 漏泄漏电流。

公开(公告)号：US5972748A

公开(公告)日：1999-10-26

申请号：US969963

申请日：1997-11-25

申请人： Hiromi Itoh ,  Tomonori Okudaira ,  Keiichiro Kashihara

发明人： Hiromi Itoh ,  Tomonori Okudaira ,  Keiichiro Kashihara

IPC分类号： H01L27/10 ,  H01L27/108 ,  H01L21/8242

CPC分类号： H01L27/10808

摘要： A first interlayer insulating film having a second contact hole is formed on a main surface of a semiconductor substrate 1 in a peripheral circuitry. A second plug electrode of the same material as a first plug electrode in a memory cell array is formed in the second contact hole. A pad layer is formed over the second plug electrode and a top surface of the first interlayer insulating film. The pad layer and a capacitor lower electrode are made of the same material. The pad layer is covered with the second interlayer insulating film. A third contact hole is formed at a portion of the second interlayer insulating film located above the pad layer. A first aluminum interconnection layer is formed in the third contact hole. Thereby, a contact can be formed easily between the interconnection layer and the main surface of the semiconductor substrate in the peripheral circuitry of a DRAM, and a manufacturing process can be simplified.

摘要翻译： 具有第二接触孔的第一层间绝缘膜形成在外围电路中的半导体衬底1的主表面上。 在第二接触孔中形成有与存储单元阵列中的第一插头电极相同材料的第二插头电极。 在第二插头电极和第一层间绝缘膜的顶表面上形成衬垫层。 焊盘层和电容器下电极由相同的材料制成。 衬垫层被第二层间绝缘膜覆盖。 在位于焊盘层上方的第二层间绝缘膜的一部分处形成第三接触孔。 在第三接触孔中形成第一铝互连层。 因此，可以在DRAM的外围电路中的互连层和半导体衬底的主表面之间容易地形成接触，并且可以简化制造工艺。

公开(公告)号：US5534458A

公开(公告)日：1996-07-09

申请号：US442925

申请日：1995-05-17

申请人： Tomonori Okudaira ,  Takeharu Kuroiwa ,  Nobuo Fujiwara ,  Keiichiro Kashihara

发明人： Tomonori Okudaira ,  Takeharu Kuroiwa ,  Nobuo Fujiwara ,  Keiichiro Kashihara

IPC分类号： H01L21/28 ,  H01L21/02 ,  H01L21/3205 ,  H01L21/768 ,  H01L21/822 ,  H01L21/8242 ,  H01L21/8246 ,  H01L23/522 ,  H01L27/04 ,  H01L27/105 ,  H01L21/70 ,  H01L27/00

CPC分类号： H01L27/10852 ,  H01L21/3205 ,  H01L28/40 ,  H01L28/55 ,  Y10S257/915 ,  Y10S438/978

摘要： According to a semiconductor device and a method of manufacturing thereof, a sidewall spacer is formed at a sidewall of a contact hole, in a recess portion defined by the sidewall of the contact hole and a buried conductive layer, having a film thickness gradually increasing from a top face corner of an interlayer insulation film to the surface of the buried conductive layer. Therefore, a semiconductor device that can achieve favorable breakdown voltage and anti-leak characteristics between a lower electrode layer and an upper electrode layer forming a capacitor of a DRAM.

摘要翻译： 根据半导体器件及其制造方法，在由接触孔的侧壁限定的凹部和埋入导电层的接触孔的侧壁处形成侧壁间隔物，其中膜厚度从 层间绝缘膜的顶面角到掩埋导电层的表面。 因此，可以在形成DRAM的电容器的下电极层和上电极层之间实现良好的击穿电压和防漏电特性的半导体装置。

公开(公告)号：US5459345A

公开(公告)日：1995-10-17

申请号：US264092

申请日：1994-06-22

申请人： Tomonori Okudaira ,  Keiichiro Kashihara

发明人： Tomonori Okudaira ,  Keiichiro Kashihara

IPC分类号： H01L27/04 ,  H01L21/822 ,  H01L21/8242 ,  H01L21/8246 ,  H01L27/105 ,  H01L27/00

CPC分类号： H01L27/10852

摘要： An object of the invention is to provide a semiconductor device which has a capacitor having good anti-leak characteristics and good breakdown voltage characteristics and is suitable to high integration. Source/drain regions (25) are formed at a surface of a silicon substrate (31). Interlayer insulating films (1) and (3) having contact holes (1a) and (3a), through which a surfaces of the source/drain region is partially exposed, is formed on the surface of silicon substrate (31). Contact holes (1a) and (3a) are filled with plug layer (9a). A capacitor (20) having a highly dielectric film (15) is formed such that it is electrically connected to source/drain region (25) through plug layer (9a). The interlayer insulating film is formed of a two-layer structure including a silicon oxide film (1) and a silicon nitride film (3). Silicon nitride film (3) and plug layer (9a) have the top surfaces flush with each other.

摘要翻译： 本发明的目的是提供一种半导体器件，其具有具有良好的防漏电特性和良好的击穿电压特性的电容器，并且适用于高集成度。 源极/漏极区（25）形成在硅衬底（31）的表面。 在硅衬底（31）的表面上形成具有接触孔（1a）和（3a）的层间绝缘膜（1）和（3），源极/漏极区域的表面部分露出。 接触孔（1a）和（3a）填充有塞层（9a）。 具有高电介质膜（15）的电容器（20）形成为通过插塞层（9a）与源极/漏极区域（25）电连接。 层间绝缘膜由包括氧化硅膜（1）和氮化硅膜（3）的两层结构形成。 氮化硅膜（3）和插塞层（9a）的上表面彼此齐平。

公开(公告)号：US08338247B2

公开(公告)日：2012-12-25

申请号：US12720174

申请日：2010-03-09

申请人： Tadashi Yamaguchi ,  Toshiaki Tsutsumi ,  Satoshi Ogino ,  Kazumasa Yonekura ,  Kenji Kawai ,  Yoshihiro Miyagawa ,  Tomonori Okudaira ,  Keiichiro Kashihara ,  Kotaro Kihara

发明人： Tadashi Yamaguchi ,  Toshiaki Tsutsumi ,  Satoshi Ogino ,  Kazumasa Yonekura ,  Kenji Kawai ,  Yoshihiro Miyagawa ,  Tomonori Okudaira ,  Keiichiro Kashihara ,  Kotaro Kihara

IPC分类号： H01L27/092 ,  H01L21/8238

CPC分类号： H01L21/823835 ,  H01L21/823807 ,  H01L21/823814 ,  H01L29/7843

摘要： To improve the performance of semiconductor devices. Over an n+-type semiconductor region for source/drain of an n-channel type MISFET and a first gate electrode, and over a p+-type semiconductor region for source/drain of a p-channel type MISFET and a second gate electrode, which are formed over a semiconductor substrate, a metal silicide layer including nickel platinum silicide is formed by a salicide process. After that, a tensile stress film is formed over the whole face of the semiconductor substrate, and then the tensile stress film over the p-channel type MISFET is removed by dry-etching, and, after a compression stress film is formed over the whole face of the semiconductor substrate, the compression stress film over the n-channel type MISFET is removed by dry-etching. The Pt concentration in the metal silicide layer is highest at the surface, and becomes lower as the depth from the surface increases.

摘要翻译： 提高半导体器件的性能。 在用于n沟道型MISFET和第一栅电极的源极/漏极的n +型半导体区域上，以及用于p沟道型MISFET和第二栅电极的源极/漏极的p +型半导体区域上，其中 形成在半导体衬底上，通过自对准硅化物工艺形成包括镍铂硅化物的金属硅化物层。 之后，在半导体基板的整个面上形成拉伸应力膜，然后通过干法蚀刻去除p沟道型MISFET上的拉伸应力膜，并且在整个压电应力膜形成之后 在半导体衬底的表面上，通过干蚀刻去除n沟道型MISFET上的压缩应力膜。 金属硅化物层中的Pt浓度在表面处最高，并且随着从表面的深度增加而变低。