利索-全球专利检索

  1. 登录
  2. 注册

搜索结果

34 条记录 (耗时 0.017 秒)

    Method of manufacturing a semiconductor memory device
    1.
    发明授权
    Method of manufacturing a semiconductor memory device 失效
    制造半导体存储器件的方法

    公开(公告)号：US5753527A

    公开(公告)日：1998-05-19

    申请号：US613555

    申请日：1996-03-11

    申请人： Hiromi Itoh ,  Tomonori Okudaira ,  Keiichiro Kashihara

    发明人： Hiromi Itoh ,  Tomonori Okudaira ,  Keiichiro Kashihara

    IPC分类号： H01L27/10 ,  H01L27/108 ,  H01L21/70

    CPC分类号： H01L27/10808

    摘要： A first interlayer insulating film having a second contact hole is formed on a main surface of a semiconductor substrate 1 in a peripheral circuitry. A second plug electrode of the same material as a first plug electrode in a memory cell array is formed in the second contact hole. A pad layer is formed over the second plug electrode and a top surface of the first interlayer insulating film. The pad layer and a capacitor lower electrode are made of the same material. The pad layer is covered with the second interlayer insulating film. A third contact hole is formed at a portion of the second interlayer insulating film located above the pad layer. A first aluminum interconnection layer is formed in the third contact hole. Thereby, a contact can be formed easily between the interconnection layer and the main surface of the semiconductor substrate in the peripheral circuitry of a DRAM, and a manufacturing process can be simplified.

    摘要翻译： 具有第二接触孔的第一层间绝缘膜形成在外围电路中的半导体衬底1的主表面上。 在第二接触孔中形成有与存储单元阵列中的第一插头电极相同材料的第二插头电极。 在第二插头电极和第一层间绝缘膜的顶表面上形成衬垫层。 焊盘层和电容器下电极由相同的材料制成。 衬垫层被第二层间绝缘膜覆盖。 在位于焊盘层上方的第二层间绝缘膜的一部分处形成第三接触孔。 在第三接触孔中形成第一铝互连层。 因此，可以在DRAM的外围电路中的互连层和半导体衬底的主表面之间容易地形成接触，并且可以简化制造工艺。

    Electronic device using zirconate titanate and barium titanate ferroelectrics in insulating layer
    2.
    发明授权
    Electronic device using zirconate titanate and barium titanate ferroelectrics in insulating layer 失效
    在绝缘层中使用钛酸钛酸锂和钛酸钡铁电体的电子器件

    公开(公告)号：US5572052A

    公开(公告)日：1996-11-05

    申请号：US374890

    申请日：1995-01-19

    申请人： Keiichiro Kashihara ,  Tomonori Okudaira ,  Hiromi Itoh

    发明人： Keiichiro Kashihara ,  Tomonori Okudaira ,  Hiromi Itoh

    IPC分类号： H01L27/115 ,  H01L29/78 ,  H01L29/92 ,  H01L29/94 ,  G11C11/22 ,  H01G4/06 ,  H01G4/20

    CPC分类号： H01L27/11502 ,  H01L29/78391 ,  H01L29/92 ,  H01L29/94

    摘要： In an electronic device using lead zirconate titanate (PZT) or lanthanum lead zirconate titanate (PLZT) as the main insulating material, a PZT film or a PLZT film is formed on a sub-insulating layer consisting essentially of lead titanate, lanthanum lead titanate, barium titanate, strontium titanate, barium strontium titanate, lead zirconate, or lanthanum lead zirconate. In an MIS structure, a semiconductor, the sub-insulating layer, the PZT film and metal are deposited in order. In a capacitor, the sub-insulating layer and the PZT film are sandwiched between a pair of electrodes. The sub-insulating layer improves crystallinity of PZT or PLZT, and the dielectric constant. An oxide of Pb, La, Zr or Ti can be added as the sub-insulating layer in order to further suppress current leakage.

    摘要翻译： 在使用锆钛酸铅（PZT）或锆钛酸镧铅（PLZT）作为主要绝缘材料的电子器件中，在主要由钛酸铅，钛酸镧铅，钛酸铅等构成的基础绝缘层上形成PZT膜或PLZT膜， 钛酸钡，钛酸锶，钛酸锶钡，锆酸铅或锆酸镧铅。 在MIS结构中，依次沉积半导体，次绝缘层，PZT膜和金属。 在电容器中，副绝缘层和PZT膜夹在一对电极之间。 亚绝缘层提高了PZT或PLZT的结晶度和介电常数。 可以添加Pb，La，Zr或Ti的氧化物作为副绝缘层，以进一步抑制电流泄漏。

    Semiconductor memory device
    3.
    发明授权
    Semiconductor memory device 失效
    半导体存储器件

    公开(公告)号：US5519237A

    公开(公告)日：1996-05-21

    申请号：US264117

    申请日：1994-06-22

    申请人： Hiromi Itoh ,  Tomonori Okudaira ,  Keiichiro Kashihara

    发明人： Hiromi Itoh ,  Tomonori Okudaira ,  Keiichiro Kashihara

    IPC分类号： H01L27/10 ,  H01L27/108 ,  H01L29/68

    CPC分类号： H01L27/10808

    摘要： A first interlayer insulating film having a second contact hole is formed on a main surface of a semiconductor substrate 1 in a peripheral circuitry. A second plug electrode of the same material as a first plug electrode in a memory cell array is formed in the second contact hole. A pad layer is formed over the second plug electrode and a top surface of the first interlayer insulating film. The pad layer and a capacitor lower electrode are made of the same material. The pad layer is covered with the second interlayer insulating film. A third contact hole is formed at a portion of the second interlayer insulating film located above the pad layer. A first aluminum interconnection layer is formed in the third contact hole. Thereby, a contact can be formed easily between the interconnection layer and the main surface of the semiconductor substrate in the peripheral circuitry of a DRAM, and a manufacturing process can be simplified.

    摘要翻译： 具有第二接触孔的第一层间绝缘膜形成在外围电路中的半导体衬底1的主表面上。 在第二接触孔中形成有与存储单元阵列中的第一插头电极相同材料的第二插头电极。 在第二插头电极和第一层间绝缘膜的顶表面上形成衬垫层。 焊盘层和电容器下电极由相同的材料制成。 衬垫层被第二层间绝缘膜覆盖。 在位于焊盘层上方的第二层间绝缘膜的一部分处形成第三接触孔。 在第三接触孔中形成第一铝互连层。 因此，可以在DRAM的外围电路中的互连层和半导体衬底的主表面之间容易地形成接触，并且可以简化制造工艺。

    Capacitor manufacturing method having dielectric formed before electrode
    4.
    发明授权
    Capacitor manufacturing method having dielectric formed before electrode 失效
    在电极之前形成电介质的电容器制造方法

    公开(公告)号：US06746876B2

    公开(公告)日：2004-06-08

    申请号：US10310765

    申请日：2002-12-06

    申请人： Hiromi Itoh ,  Yoshikazu Tsunemine ,  Keiichiro Kashihara ,  Akie Yutani ,  Tomonori Okudaira

    发明人： Hiromi Itoh ,  Yoshikazu Tsunemine ,  Keiichiro Kashihara ,  Akie Yutani ,  Tomonori Okudaira

    IPC分类号： H01L218242

    CPC分类号： H01L28/55 ,  H01L28/91

    摘要： A method for manufacturing a capacitor is provided which can form a lower electrode having a high aspect ratio without suffering deterioration of the capacitor electric characteristics even when a platinum-group metal is adopted as the material of the lower electrode and a metal oxide having a high dielectric constant is adopted as the material of the dielectric film. Holes (8) that reach contact plugs (2) are formed in an insulating film (7). Then a dielectric film (9) is formed on the surfaces of the holes (8). Next the dielectric film (9) on the bottoms of the holes (8) are etched away to form holes (18) reaching the contact plugs (2). Lower electrodes (11) are then formed to fill the holes (8) and (18).

    摘要翻译： 提供了一种用于制造电容器的方法，即使当采用铂族金属作为下电极的材料时，也可形成具有高纵横比的下电极，而不会降低电容器的电特性，并且具有高的金属氧化物 采用介电常数作为电介质膜的材料。 到达接触塞（2）的孔（8）形成在绝缘膜（7）中。 然后在孔（8）的表面上形成介电膜（9）。 接下来，蚀刻掉孔（8）的底部上的电介质膜（9），以形成到达接触塞（2）的孔（18）。 然后形成下电极（11）以填充孔（8）和（18）。

    Semiconductor memory device and method of manufacturing the same
    5.
    发明授权
    Semiconductor memory device and method of manufacturing the same 失效
    半导体存储器件及其制造方法

    公开(公告)号：US5972748A

    公开(公告)日：1999-10-26

    申请号：US969963

    申请日：1997-11-25

    申请人： Hiromi Itoh ,  Tomonori Okudaira ,  Keiichiro Kashihara

    发明人： Hiromi Itoh ,  Tomonori Okudaira ,  Keiichiro Kashihara

    IPC分类号： H01L27/10 ,  H01L27/108 ,  H01L21/8242

    CPC分类号： H01L27/10808

    摘要： A first interlayer insulating film having a second contact hole is formed on a main surface of a semiconductor substrate 1 in a peripheral circuitry. A second plug electrode of the same material as a first plug electrode in a memory cell array is formed in the second contact hole. A pad layer is formed over the second plug electrode and a top surface of the first interlayer insulating film. The pad layer and a capacitor lower electrode are made of the same material. The pad layer is covered with the second interlayer insulating film. A third contact hole is formed at a portion of the second interlayer insulating film located above the pad layer. A first aluminum interconnection layer is formed in the third contact hole. Thereby, a contact can be formed easily between the interconnection layer and the main surface of the semiconductor substrate in the peripheral circuitry of a DRAM, and a manufacturing process can be simplified.

    摘要翻译： 具有第二接触孔的第一层间绝缘膜形成在外围电路中的半导体衬底1的主表面上。 在第二接触孔中形成有与存储单元阵列中的第一插头电极相同材料的第二插头电极。 在第二插头电极和第一层间绝缘膜的顶表面上形成衬垫层。 焊盘层和电容器下电极由相同的材料制成。 衬垫层被第二层间绝缘膜覆盖。 在位于焊盘层上方的第二层间绝缘膜的一部分处形成第三接触孔。 在第三接触孔中形成第一铝互连层。 因此，可以在DRAM的外围电路中的互连层和半导体衬底的主表面之间容易地形成接触，并且可以简化制造工艺。

    Semiconductor device and manufacturing method thereof
    8.
    发明授权
    Semiconductor device and manufacturing method thereof 有权
    半导体装置及其制造方法

    公开(公告)号：US08148248B2

    公开(公告)日：2012-04-03

    申请号：US13053733

    申请日：2011-03-22

    申请人： Toshiaki Tsutsumi ,  Tomonori Okudaira ,  Keiichiro Kashihara ,  Tadashi Yamaguchi

    发明人： Toshiaki Tsutsumi ,  Tomonori Okudaira ,  Keiichiro Kashihara ,  Tadashi Yamaguchi

    IPC分类号： H01L21/3205 ,  H01L21/4763

    CPC分类号： H01L23/485 ,  H01L21/28518 ,  H01L2924/0002 ,  H01L2924/00

    摘要： There is provided a semiconductor device having a metal silicide layer which can suppress the malfunction and the increase in power consumption of the device. The semiconductor device has a semiconductor substrate containing silicon and having a main surface, first and second impurity diffusion layers formed in the main surface of the semiconductor substrate, a metal silicide formed over the second impurity diffusion layer, and a silicon nitride film and a first interlayer insulation film sequentially stacked over the metal silicide. In the semiconductor device, a contact hole penetrating through the silicon nitride film and the first interlayer insulation film, and reaching the surface of the metal silicide is formed. The thickness of a portion of the metal silicide situated immediately under the contact hole is smaller than the thickness of a portion of the metal silicide situated around the contact hole.

    摘要翻译： 提供了具有金属硅化物层的半导体器件，其可以抑制器件的故障和功率消耗的增加。 半导体器件具有包含硅并具有主表面的半导体衬底，形成在半导体衬底的主表面中的第一和第二杂质扩散层，形成在第二杂质扩散层上的金属硅化物，以及氮化硅膜和第一 层间绝缘膜依次层叠在金属硅化物上。 在半导体器件中，形成穿过氮化硅膜和第一层间绝缘膜并到达金属硅化物表面的接触孔。 位于接触孔正下方的金属硅化物的一部分的厚度小于位于接触孔周围的金属硅化物的一部分的厚度。