公开(公告)号：US20060227648A1

公开(公告)日：2006-10-12

申请号：US11399397

申请日：2006-04-07

申请人： Norifumi Kameshiro ,  Riichiro Takemura ,  Tomoyuki Ishii

发明人： Norifumi Kameshiro ,  Riichiro Takemura ,  Tomoyuki Ishii

IPC分类号： G11C8/00

CPC分类号： G11C11/405 ,  G11C7/18 ,  G11C11/4097 ,  G11C2211/4013 ,  H01L27/0207 ,  H01L27/108

摘要： In a two-transistor gain cell structure, a semiconductor memory device capable of stable reading without malfunction and having small-area memory cells is provided. In a two-transistor gain cell memory having a write transistor and a read transistor, a write word line, a read word line, a write bit line, and a read bit line are separately provided, and voltages to be applied are independently set. Furthermore, a memory cell is connected to the same read word line and write bit line as those of an adjacent memory cell.

摘要翻译： 在双晶体管增益单元结构中，提供了能够稳定读取而没有故障并且具有小面积存储单元的半导体存储器件。 在具有写晶体管和读晶体管的双晶体管增益单元存储器中，分别提供写字线，读字线，写位线和读位线，并且独立地设置要施加的电压。 此外，存储单元连接到与相邻存储单元相同的读字线和写位线。

公开(公告)号：US07859889B2

公开(公告)日：2010-12-28

申请号：US12186204

申请日：2008-08-05

申请人： Norifumi Kameshiro ,  Riichiro Takemura ,  Tomoyuki Ishii

发明人： Norifumi Kameshiro ,  Riichiro Takemura ,  Tomoyuki Ishii

IPC分类号： G11C11/24

CPC分类号： G11C11/405 ,  G11C7/18 ,  G11C11/4097 ,  G11C2211/4013 ,  H01L27/0207 ,  H01L27/108

摘要： In a two-transistor gain cell structure, a semiconductor memory device capable of stable reading without malfunction and having small-area memory cells is provided. In a two-transistor gain cell memory having a write transistor and a read transistor, a write word line, a read word line, a write bit line, and a read bit line are separately provided, and voltages to be applied are independently set. Furthermore, a memory cell is connected to the same read word line and write bit line as those of an adjacent memory cell.

摘要翻译： 在双晶体管增益单元结构中，提供了能够稳定读取而没有故障并且具有小面积存储单元的半导体存储器件。 在具有写晶体管和读晶体管的双晶体管增益单元存储器中，分别提供写字线，读字线，写位线和读位线，并且独立地设置要施加的电压。 此外，存储单元连接到与相邻存储单元相同的读字线和写位线。

公开(公告)号：US20080285325A1

公开(公告)日：2008-11-20

申请号：US12186204

申请日：2008-08-05

申请人： NORIFUMI KAMESHIRO ,  Riichiro Takemura ,  Tomoyuki Ishii

发明人： NORIFUMI KAMESHIRO ,  Riichiro Takemura ,  Tomoyuki Ishii

IPC分类号： G11C5/02 ,  G11C5/06

CPC分类号： G11C11/405 ,  G11C7/18 ,  G11C11/4097 ,  G11C2211/4013 ,  H01L27/0207 ,  H01L27/108

摘要： In a two-transistor gain cell structure, a semiconductor memory device capable of stable reading without malfunction and having small-area memory cells is provided. In a two-transistor gain cell memory having a write transistor and a read transistor, a write word line, a read word line, a write bit line, and a read bit line are separately provided, and voltages to be applied are independently set. Furthermore, a memory cell is connected to the same read word line and write bit line as those of an adjacent memory cell.

摘要翻译： 在双晶体管增益单元结构中，提供了能够稳定读取而没有故障并且具有小面积存储单元的半导体存储器件。 在具有写晶体管和读晶体管的双晶体管增益单元存储器中，分别提供写字线，读字线，写位线和读位线，并且独立地设置要施加的电压。 此外，存储单元连接到与相邻存储单元相同的读字线和写位线。

公开(公告)号：US5684734A

公开(公告)日：1997-11-04

申请号：US600678

申请日：1996-02-13

申请人： Tomoyuki Ishii ,  Kazuo Yano ,  Koichi Seki ,  Toshiyuki Mine ,  Takashi Kobayashi

发明人： Tomoyuki Ishii ,  Kazuo Yano ,  Koichi Seki ,  Toshiyuki Mine ,  Takashi Kobayashi

IPC分类号： H01L27/115 ,  H01L27/12 ,  H01L29/68 ,  H01L29/788 ,  G11C17/00

CPC分类号： H01L29/7887 ,  H01L27/115 ,  H01L27/1203 ,  H01L29/685 ,  H01L29/7883 ,  Y10S438/962

摘要： A semiconductor memory element is disclosed which can share the terminals easily among a plurality of memory elements and can pass a high current and which is strong against the noises. In order to accomplish this a control electrode is formed to cover the entirety of thin film regions connecting low-resistance regions. As a result, the element can have a small size and can store information with high density. Thus, a highly integrated, low power consumption non-volatile memory device can be realized with reduced size.

摘要翻译： 公开了一种半导体存储元件，其可以在多个存储元件中容易地共享端子，并且可以通过高电流并且抵抗噪声。 为了实现这一点，形成控制电极以覆盖连接低电阻区域的整个薄膜区域。 因此，该元件可以具有小尺寸并且可以高密度地存储信息。 因此，可以以减小的尺寸实现高度集成的低功耗非易失性存储器件。

公开(公告)号：US06876023B2

公开(公告)日：2005-04-05

申请号：US10158851

申请日：2002-06-03

申请人： Tomoyuki Ishii ,  Kazuo Yano ,  Toshiyuki Mine

发明人： Tomoyuki Ishii ,  Kazuo Yano ,  Toshiyuki Mine

IPC分类号： H01L21/8247 ,  G11C16/04 ,  H01L21/8242 ,  H01L21/8244 ,  H01L27/105 ,  H01L27/108 ,  H01L27/11 ,  H01L27/115 ,  H01L27/12 ,  H01L29/66 ,  H01L29/786 ,  H01L29/788 ,  H01L29/792

CPC分类号： G11C16/0433 ,  H01L27/105 ,  H01L27/108 ,  H01L27/10873 ,  H01L27/12 ,  H01L27/1203 ,  H01L29/78642

摘要： A semiconductor memory element subject to a threshold voltage controlling method other than those based on low leak currents or on the implantation of impurities. Such semiconductor elements are used to form semiconductor memory elements that are employed in scaled-down structures and are conducive to high-speed write operations thanks to a sufficiently prolonged refresh cycle. These semiconductor memory elements are in turn used to constitute a semiconductor memory device. A very thin semiconductor film is used as channels so that leak currents are reduced by the quantum-mechanical containment effect in the direction of film thickness. An amount of electrical charges in each charge accumulating region is used to change conductance between a source and a drain region of each read transistor structure, the conductance change being utilized for data storage. A channel of a transistor for electrically charging or discharging each charge accumulating region is made of a semiconductor film 5 nm thick at most. The arrangement affords both high-speed data write performance and an extended data retention time. The invention provides a high-speed, power-saving semiconductor device of high integration particularly advantageous for producing a small-scale system of low-power dissipation.

摘要翻译： 除了基于低泄漏电流或杂质注入以外的阈值电压控制方法的半导体存储元件。 这样的半导体元件用于形成在缩小结构中使用的半导体存储器元件，并且由于足够长的刷新周期而有利于高速写入操作。 这些半导体存储元件又用于构成半导体存储器件。 使用非常薄的半导体膜作为通道，使得通过膜厚度方向的量子力学容纳效应来降低泄漏电流。 使用每个电荷累积区域中的电荷量来改变每个读取晶体管结构的源区和漏区之间的电导，所述电导变化用于数据存储。 用于对每个电荷累积区进行充电或放电的晶体管的沟道由最多为5nm厚的半导体膜制成。 该方案具有高速数据写入性能和扩展数据保留时间。 本发明提供了高集成度的高速，省电的半导体器件，特别有利于生产低功耗的小规模系统。

公开(公告)号：US06337293B1

公开(公告)日：2002-01-08

申请号：US09332445

申请日：1999-06-14

申请人： Tomoyuki Ishii ,  Kazuo Yano ,  Koichi Seki ,  Toshiyuki Mine ,  Takashi Kobayashi

发明人： Tomoyuki Ishii ,  Kazuo Yano ,  Koichi Seki ,  Toshiyuki Mine ,  Takashi Kobayashi

IPC分类号： H01L2100

CPC分类号： H01L29/7887 ,  H01L27/115 ,  H01L27/1203 ,  H01L29/685 ,  H01L29/7883 ,  Y10S438/962

摘要： A semiconductor quantum memory element is disclosed which can share the terminals easily among a plurality of memory elements and can pass a high current and which is strong against noise. In order to accomplish this a control electrode is formed so as to cover the entirety of thin film regions connecting low-resistance regions. As a result, the element can have a small size and can store information with high density. Thus, a highly integrated, low power consumption non-volatile memory device can be realized with reduced size. A method of forming a memory element is also disclosed including performing the following steps of forming a first insulating layer, a second insulating layer, a first conductive layer and a layer of amorphous silicon. The amorphous silicon layer is crystallized to a polycrystalline silicon film. Semiconductor drains are deposited to form charge trapping and storage regions. A fourth insulating layer is deposited over the drains and a second conductive layer is deposited over a layer of silicon dioxide to form a control electrode of the memory element.

摘要翻译： 公开了一种半导体量子存储器元件，其可以容易地在多个存储元件之间共享端子，并且可以通过高电流并且抵抗噪声。 为了实现这一点，形成控制电极以覆盖连接低电阻区域的整个薄膜区域。 因此，该元件可以具有小尺寸并且可以高密度地存储信息。 因此，可以以减小的尺寸实现高度集成的低功耗非易失性存储器件。 还公开了一种形成存储元件的方法，包括执行以下步骤：形成第一绝缘层，第二绝缘层，第一导电层和非晶硅层。 非晶硅层结晶成多晶硅膜。 沉积半导体漏极以形成电荷捕获和存储区域。 在漏极上沉积第四绝缘层，并且在二氧化硅层上沉积第二导电层以形成存储元件的控制电极。

公开(公告)号：US5960266A

公开(公告)日：1999-09-28

申请号：US878206

申请日：1997-06-18

申请人： Tomoyuki Ishii ,  Kazuo Yano ,  Koichi Seki ,  Toshiyuki Mine ,  Takashi Kobayashi

发明人： Tomoyuki Ishii ,  Kazuo Yano ,  Koichi Seki ,  Toshiyuki Mine ,  Takashi Kobayashi

IPC分类号： H01L27/115 ,  H01L27/12 ,  H01L29/68 ,  H01L29/788 ,  H01L21/00 ,  H01L21/31 ,  H01L21/469 ,  H01L21/84

CPC分类号： H01L29/7887 ,  H01L27/115 ,  H01L27/1203 ,  H01L29/685 ,  H01L29/7883 ,  Y10S438/962

摘要： A quantum semiconductor memory element is disclosed which can share the terminals easily among a plurality of memory elements and can pass a high current and which is resistant to interference from noises. In order to accomplish this a control electrode is formed to cover the entirety of thin film regions connecting low-resistance regions. As a result, the element can have a small size and can store information with high density. Thus, a highly integrated, low power consumption non-volatile quantum memory device can be realized with reduced size.

摘要翻译： 公开了一种量子半导体存储元件，其可以容易地在多个存储元件之间共享端子，并且可以通过高电流并且能够抵抗来自噪声的干扰。 为了实现这一点，形成控制电极以覆盖连接低电阻区域的整个薄膜区域。 因此，该元件可以具有小尺寸并且可以高密度地存储信息。 因此，可以以减小的尺寸实现高度集成的低功耗非易失性量子存储器件。

公开(公告)号：US07969760B2

公开(公告)日：2011-06-28

申请号：US11790590

申请日：2007-04-26

申请人： Tomoyuki Ishii ,  Yoshitaka Sasago ,  Hideaki Kurata ,  Toshiyuki Mine

发明人： Tomoyuki Ishii ,  Yoshitaka Sasago ,  Hideaki Kurata ,  Toshiyuki Mine

IPC分类号： G11C5/06

CPC分类号： H01L27/0207 ,  H01L27/115 ,  H01L27/11519 ,  H01L27/11521 ,  H01L27/11524

摘要： The invention provides a voltage applying structure having a reduced area penalty with respect to a data line. A wiring forming a global data line and a local data line formed in a p-type well region are connected via a select transistor. Two select lines are formed on a gate electrode of the select transistor. One select line is electrically connected to the gate electrode of the select transistor, however, the other select line is not connected to the select transistor. That is, an insulator film is formed between the select line and the gate electrode. As mentioned above, two select lines shorter than a gate length are provided on one select transistor. The select line is structured such as to be connected to the other select transistor.

摘要翻译： 本发明提供一种相对于数据线具有减小的面积损失的电压施加结构。 形成在p型阱区中的全局数据线和局部数据线的布线经由选择晶体管连接。 在选择晶体管的栅电极上形成两条选择线。 一个选择线电连接到选择晶体管的栅电极，然而另一选择线不连接到选择晶体管。 也就是说，在选择线和栅电极之间形成绝缘膜。 如上所述，在一个选择晶体管上设置两条比栅极长度短的选择线。 选择线被构造成连接到另一个选择晶体管。

公开(公告)号：US20070285983A1

公开(公告)日：2007-12-13

申请号：US11790590

申请日：2007-04-26

申请人： Tomoyuki Ishii ,  Yoshitaka Sasago ,  Hideaki Kurata ,  Toshiyuki Mine

发明人： Tomoyuki Ishii ,  Yoshitaka Sasago ,  Hideaki Kurata ,  Toshiyuki Mine

IPC分类号： G11C11/34 ,  H01L21/336

CPC分类号： H01L27/0207 ,  H01L27/115 ,  H01L27/11519 ,  H01L27/11521 ,  H01L27/11524

摘要： The invention provides a voltage applying structure having a reduced area penalty with respect to a data line. A wiring forming a global data line and a local data line formed in a p-type well region are connected via a select transistor. Two select lines are formed on a gate electrode of the select transistor. One select line is electrically connected to the gate electrode of the select transistor, however, the other select line is not connected to the select transistor. That is, an insulator film is formed between the select line and the gate electrode. As mentioned above, two select lines shorter than a gate length are provided on one select transistor. The select line is structured such as to be connected to the other select transistor.

摘要翻译： 本发明提供一种相对于数据线具有减小的面积损失的电压施加结构。 形成在p型阱区中的全局数据线和局部数据线的布线经由选择晶体管连接。 在选择晶体管的栅电极上形成两条选择线。 一个选择线电连接到选择晶体管的栅电极，然而另一选择线不连接到选择晶体管。 也就是说，在选择线和栅电极之间形成绝缘膜。 如上所述，在一个选择晶体管上设置两条比栅极长度短的选择线。 选择线被构造成连接到另一个选择晶体管。

公开(公告)号：US06576943B1

公开(公告)日：2003-06-10

申请号：US09512827

申请日：2000-02-25

申请人： Tomoyuki Ishii ,  Kazuo Yano ,  Toshiyuki Mine

发明人： Tomoyuki Ishii ,  Kazuo Yano ,  Toshiyuki Mine

IPC分类号： H01L27108

CPC分类号： G11C16/0433 ,  H01L27/105 ,  H01L27/108 ,  H01L27/10873 ,  H01L27/12 ,  H01L27/1203 ,  H01L29/78642

摘要： A very thin semiconductor film is used for channels of semiconductor memory elements such that leak currents are reduced by the quantum-mechanical containment effect in the direction of film thickness. The amount of electrical charge accumulated in each charge accumulating region is used to change the conductance between a source region and a drain region of each read transistor structure. This conductance change is utilized for data storage. The thickness of the channel of the write transistor structure is preferably no more than 5 nm. According to one embodiment, the channel of the write transistor is formed by a semiconductor film deposited on a surface intersecting a principal plane of the substrate.

摘要翻译： 非常薄的半导体膜用于半导体存储元件的通道，使得漏电流通过膜厚度方向的量子力学容纳效应而降低。 使用在每个电荷累积区域中累积的电荷量来改变每个读取的晶体管结构的源极区域和漏极区域之间的电导。 该电导变化用于数据存储。 写入晶体管结构的沟道的厚度优选不大于5nm。 根据一个实施例，写入晶体管的沟道由沉积在与衬底的主平面相交的表面上的半导体膜形成。