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    Gain cell type non-volatile memory having charge accumulating region charged or discharged by channel current from a thin film channel path
    2.
    发明授权
    Gain cell type non-volatile memory having charge accumulating region charged or discharged by channel current from a thin film channel path 失效
    具有从薄膜通道路径通过通道电流充电或放电的电荷累积区域的增益单元型非易失性存储器

    公开(公告)号：US06876023B2

    公开(公告)日：2005-04-05

    申请号：US10158851

    申请日：2002-06-03

    申请人： Tomoyuki Ishii ,  Kazuo Yano ,  Toshiyuki Mine

    发明人： Tomoyuki Ishii ,  Kazuo Yano ,  Toshiyuki Mine

    IPC分类号： H01L21/8247 ,  G11C16/04 ,  H01L21/8242 ,  H01L21/8244 ,  H01L27/105 ,  H01L27/108 ,  H01L27/11 ,  H01L27/115 ,  H01L27/12 ,  H01L29/66 ,  H01L29/786 ,  H01L29/788 ,  H01L29/792

    CPC分类号： G11C16/0433 ,  H01L27/105 ,  H01L27/108 ,  H01L27/10873 ,  H01L27/12 ,  H01L27/1203 ,  H01L29/78642

    摘要： A semiconductor memory element subject to a threshold voltage controlling method other than those based on low leak currents or on the implantation of impurities. Such semiconductor elements are used to form semiconductor memory elements that are employed in scaled-down structures and are conducive to high-speed write operations thanks to a sufficiently prolonged refresh cycle. These semiconductor memory elements are in turn used to constitute a semiconductor memory device. A very thin semiconductor film is used as channels so that leak currents are reduced by the quantum-mechanical containment effect in the direction of film thickness. An amount of electrical charges in each charge accumulating region is used to change conductance between a source and a drain region of each read transistor structure, the conductance change being utilized for data storage. A channel of a transistor for electrically charging or discharging each charge accumulating region is made of a semiconductor film 5 nm thick at most. The arrangement affords both high-speed data write performance and an extended data retention time. The invention provides a high-speed, power-saving semiconductor device of high integration particularly advantageous for producing a small-scale system of low-power dissipation.

    摘要翻译： 除了基于低泄漏电流或杂质注入以外的阈值电压控制方法的半导体存储元件。 这样的半导体元件用于形成在缩小结构中使用的半导体存储器元件，并且由于足够长的刷新周期而有利于高速写入操作。 这些半导体存储元件又用于构成半导体存储器件。 使用非常薄的半导体膜作为通道，使得通过膜厚度方向的量子力学容纳效应来降低泄漏电流。 使用每个电荷累积区域中的电荷量来改变每个读取晶体管结构的源区和漏区之间的电导，所述电导变化用于数据存储。 用于对每个电荷累积区进行充电或放电的晶体管的沟道由最多为5nm厚的半导体膜制成。 该方案具有高速数据写入性能和扩展数据保留时间。 本发明提供了高集成度的高速，省电的半导体器件，特别有利于生产低功耗的小规模系统。

    Method of forming a quantum memory element having a film of amorphous silicon
    3.
    发明授权
    Method of forming a quantum memory element having a film of amorphous silicon 失效
    形成具有非晶硅膜的量子存储元件的方法

    公开(公告)号：US06337293B1

    公开(公告)日：2002-01-08

    申请号：US09332445

    申请日：1999-06-14

    申请人： Tomoyuki Ishii ,  Kazuo Yano ,  Koichi Seki ,  Toshiyuki Mine ,  Takashi Kobayashi

    发明人： Tomoyuki Ishii ,  Kazuo Yano ,  Koichi Seki ,  Toshiyuki Mine ,  Takashi Kobayashi

    IPC分类号： H01L2100

    CPC分类号： H01L29/7887 ,  H01L27/115 ,  H01L27/1203 ,  H01L29/685 ,  H01L29/7883 ,  Y10S438/962

    摘要： A semiconductor quantum memory element is disclosed which can share the terminals easily among a plurality of memory elements and can pass a high current and which is strong against noise. In order to accomplish this a control electrode is formed so as to cover the entirety of thin film regions connecting low-resistance regions. As a result, the element can have a small size and can store information with high density. Thus, a highly integrated, low power consumption non-volatile memory device can be realized with reduced size. A method of forming a memory element is also disclosed including performing the following steps of forming a first insulating layer, a second insulating layer, a first conductive layer and a layer of amorphous silicon. The amorphous silicon layer is crystallized to a polycrystalline silicon film. Semiconductor drains are deposited to form charge trapping and storage regions. A fourth insulating layer is deposited over the drains and a second conductive layer is deposited over a layer of silicon dioxide to form a control electrode of the memory element.

    摘要翻译： 公开了一种半导体量子存储器元件，其可以容易地在多个存储元件之间共享端子，并且可以通过高电流并且抵抗噪声。 为了实现这一点，形成控制电极以覆盖连接低电阻区域的整个薄膜区域。 因此，该元件可以具有小尺寸并且可以高密度地存储信息。 因此，可以以减小的尺寸实现高度集成的低功耗非易失性存储器件。 还公开了一种形成存储元件的方法，包括执行以下步骤：形成第一绝缘层，第二绝缘层，第一导电层和非晶硅层。 非晶硅层结晶成多晶硅膜。 沉积半导体漏极以形成电荷捕获和存储区域。 在漏极上沉积第四绝缘层，并且在二氧化硅层上沉积第二导电层以形成存储元件的控制电极。

    Semiconductor memory device
    4.
    发明授权
    Semiconductor memory device 有权
    半导体存储器件

    公开(公告)号：US06194759B1

    公开(公告)日：2001-02-27

    申请号：US09436225

    申请日：1999-11-09

    申请人： Toshiaki Sano ,  Tomoyuki Ishii ,  Kazuo Yano ,  Toshiyuki Mine

    发明人： Toshiaki Sano ,  Tomoyuki Ishii ,  Kazuo Yano ,  Toshiyuki Mine

    IPC分类号： H01L2976

    CPC分类号： B82Y10/00 ,  G11C11/5621 ,  G11C11/5628 ,  G11C11/5635 ,  G11C11/5642 ,  G11C11/5671 ,  G11C16/0416 ,  G11C16/10 ,  G11C16/16 ,  G11C16/26 ,  G11C2216/08 ,  H01L27/115 ,  H01L29/42324 ,  H01L29/66825 ,  H01L29/7883 ,  H01L29/7888

    摘要： A memory cell with a small surface area is fabricated by forming source lines and data lines above and below and by running the channels to face up and down. The local data lines for each vertically stacked memory cell are connected to a global data line by way of separate selection by a molecular oxide semiconductor, and use of a large surface area is avoided by making joint use of peripheral circuits such as global data lines and sensing amplifiers by performing read and write operations in a timed multiplex manner. Moreover, data lines in multi-layers and memory cells (floating electrode cell) which are non-destructive with respect to readout are utilized to allow placement of memory cells at all intersecting points of word lines and data lines while having a folded data line structure. An improved noise tolerance is attained by establishing a standard threshold voltage for identical dummy cells even in any of the read verify, write verify and erase verify operations. A register to temporarily hold write data in a memory cell during writing is also used as a register to hold a flag showing that writing has ended during write verify. Also, a circuit comprised of one nMOS transistor is utilized as a means to change values on the write-end flag.

    摘要翻译： 通过在上下形成源极线和数据线，并且通过使通道正面上下而制造具有小表面积的存储单元。 每个垂直堆叠的存储单元的本地数据线通过分子氧化物半导体的单独选择连接到全局数据线，并且通过联合使用诸如全局数据线和外围电路的外围电路来避免使用大的表面积 通过以定时复用方式执行读和写操作来感测放大器。 此外，利用相对于读出非破坏性的多层和存储单元（浮动电极单元）中的数据线，以允许在字线和数据线的所有交叉点处放置存储单元，同时具有折叠的数据线结构 。 即使在读取验证，写入验证和擦除验证操作中的任何一个中，通过建立用于相同虚拟单元的标准阈值电压来获得改善的噪声容限。 在写入期间暂时保持写入数据在存储单元中的寄存器也被用作寄存器来保存写入验证期间写入结束的标志。 此外，由一个nMOS晶体管组成的电路被用作改变写入端标志的值的手段。

    Semiconductor memory device
    5.
    发明授权
    Semiconductor memory device 有权
    半导体存储器件

    公开(公告)号：US6040605A

    公开(公告)日：2000-03-21

    申请号：US236630

    申请日：1999-01-26

    申请人： Toshiaki Sano ,  Tomoyuki Ishii ,  Kazuo Yano ,  Toshiyuki Mine

    发明人： Toshiaki Sano ,  Tomoyuki Ishii ,  Kazuo Yano ,  Toshiyuki Mine

    IPC分类号： G11C11/56 ,  G11C16/04 ,  G11C16/10 ,  G11C16/16 ,  G11C16/26 ,  H01L21/336 ,  H01L27/115 ,  H01L29/423 ,  H01L29/788 ,  H01L29/76 ,  H01L29/94 ,  H01L31/062 ,  H01L31/113

    CPC分类号： B82Y10/00 ,  G11C11/5621 ,  G11C11/5628 ,  G11C11/5635 ,  G11C11/5642 ,  G11C11/5671 ,  G11C16/0416 ,  G11C16/10 ,  G11C16/16 ,  G11C16/26 ,  H01L27/115 ,  H01L29/42324 ,  H01L29/66825 ,  H01L29/7883 ,  H01L29/7888 ,  G11C2216/08

    摘要： A memory cell with a small surface area is fabricated by forming source lines and data lines above and below and by running the channels to face up and down. The local data lines for each vertically stacked memory cell are connected to a global data line by way of separate selection by a molecular oxide semiconductor, and use of a large surface area is avoided by making joint use of peripheral circuits such as global data lines and sensing amplifiers by performing read and write operations in a timed multiplex manner. Moreover, data lines in multi-layers and memory cells (floating electrode cell) which are non-destructive with respect to readout are utilized to allow placement of memory cells at all intersecting points of word lines and data lines while having a folded data line structure. An improved noise tolerance is attained by establishing a standard threshold voltage for identical dummy cells even in any of the read verify, write verify and erase verify operations. A register to temporarily hold write data in a memory cell during writing is also used as a register to hold a flag showing that writing has ended during write verify. Also, a circuit comprised of one nMOS transistor is utilized as a means to change values on the write-end flag.

    摘要翻译： 通过在上下形成源极线和数据线，并且通过使通道正面上下而制造具有小表面积的存储单元。 每个垂直堆叠的存储单元的本地数据线通过分子氧化物半导体的单独选择连接到全局数据线，并且通过联合使用诸如全局数据线和外围电路的外围电路来避免使用大的表面积 通过以定时复用方式执行读和写操作来感测放大器。 此外，利用相对于读出非破坏性的多层和存储单元（浮动电极单元）中的数据线，以允许在字线和数据线的所有交叉点处放置存储单元，同时具有折叠的数据线结构 。 即使在读取验证，写入验证和擦除验证操作中的任何一个中，通过建立用于相同虚拟单元的标准阈值电压来获得改善的噪声容限。 在写入期间暂时保持写入数据在存储单元中的寄存器也被用作寄存器来保存写入验证期间写入结束的标志。 此外，由一个nMOS晶体管组成的电路被用作改变写入端标志的值的手段。

    Semiconductor memory device
    7.
    再颁专利
    Semiconductor memory device 有权
    半导体存储器件

    公开(公告)号：USRE41868E1

    公开(公告)日：2010-10-26

    申请号：US11708145

    申请日：2007-02-20

    申请人： Toshiaki Sano ,  Tomoyuki Ishii ,  Kazuo Yano ,  Toshiyuki Mine

    发明人： Toshiaki Sano ,  Tomoyuki Ishii ,  Kazuo Yano ,  Toshiyuki Mine

    IPC分类号： H01L29/76 ,  H01L29/788

    CPC分类号： B82Y10/00 ,  G11C11/5621 ,  G11C11/5628 ,  G11C11/5635 ,  G11C11/5642 ,  G11C11/5671 ,  G11C16/0416 ,  G11C16/10 ,  G11C16/16 ,  G11C16/26 ,  G11C2216/08 ,  H01L21/28273 ,  H01L27/115 ,  H01L27/11519 ,  H01L27/11521 ,  H01L29/42324 ,  H01L29/66825 ,  H01L29/7883 ,  H01L29/7888 ,  H01L29/7889

    摘要： A memory cell with a small surface area is fabricated by forming source lines and data lines above and below and by running the channels to face up and down. The local data lines for each vertically stacked memory cell are connected to a global data line by way of separate selection by a molecular oxide semiconductor, and use of a large surface area is avoided by making joint use of peripheral circuits such as global data lines and sensing amplifiers by performing read and write operations in a timed multiplex manner. Moreover, data lines in multi-layers and memory cells (floating electrode cell) which are non-destructive with respect to readout are utilized to allow placement of memory cells at all intersecting points of word lines and data lines while having a folded data line structure. An improved noise tolerance is attained by establishing a standard threshold voltage for identical dummy cells even in any of the read verify, write verify and erase verify operations. A register to temporarily hold write data in a memory cell during writing is also used as a register to hold a flag showing that writing has ended during write verify. Also, a circuit comprised of one nMOS transistor is utilized as a means to change values on the write-end flag.

    摘要翻译： 通过在上下形成源极线和数据线，并且通过使通道正面上下而制造具有小表面积的存储单元。 每个垂直堆叠的存储单元的本地数据线通过分子氧化物半导体的单独选择连接到全局数据线，并且通过联合使用诸如全局数据线和外围电路的外围电路来避免使用大的表面积 通过以定时复用方式执行读和写操作来感测放大器。 此外，利用相对于读出非破坏性的多层和存储单元（浮动电极单元）中的数据线，以允许在字线和数据线的所有交叉点处放置存储单元，同时具有折叠的数据线结构 。 即使在读取验证，写入验证和擦除验证操作中的任何一个中，通过建立用于相同虚拟单元的标准阈值电压来获得改善的噪声容限。 在写入期间暂时保持写入数据在存储单元中的寄存器也被用作寄存器来保存写入验证期间写入结束的标志。 此外，由一个nMOS晶体管组成的电路被用作改变写入端标志的值的手段。

    Semiconductor device for reducing leak currents and controlling a threshold voltage and using a thin channel structure
    8.
    发明授权
    Semiconductor device for reducing leak currents and controlling a threshold voltage and using a thin channel structure 失效
    用于减少泄漏电流并控制阈值电压并使用薄沟道结构的半导体器件

    公开(公告)号：US06576943B1

    公开(公告)日：2003-06-10

    申请号：US09512827

    申请日：2000-02-25

    申请人： Tomoyuki Ishii ,  Kazuo Yano ,  Toshiyuki Mine

    发明人： Tomoyuki Ishii ,  Kazuo Yano ,  Toshiyuki Mine

    IPC分类号： H01L27108

    CPC分类号： G11C16/0433 ,  H01L27/105 ,  H01L27/108 ,  H01L27/10873 ,  H01L27/12 ,  H01L27/1203 ,  H01L29/78642

    摘要： A very thin semiconductor film is used for channels of semiconductor memory elements such that leak currents are reduced by the quantum-mechanical containment effect in the direction of film thickness. The amount of electrical charge accumulated in each charge accumulating region is used to change the conductance between a source region and a drain region of each read transistor structure. This conductance change is utilized for data storage. The thickness of the channel of the write transistor structure is preferably no more than 5 nm. According to one embodiment, the channel of the write transistor is formed by a semiconductor film deposited on a surface intersecting a principal plane of the substrate.

    摘要翻译： 非常薄的半导体膜用于半导体存储元件的通道，使得漏电流通过膜厚度方向的量子力学容纳效应而降低。 使用在每个电荷累积区域中累积的电荷量来改变每个读取的晶体管结构的源极区域和漏极区域之间的电导。 该电导变化用于数据存储。 写入晶体管结构的沟道的厚度优选不大于5nm。 根据一个实施例，写入晶体管的沟道由沉积在与衬底的主平面相交的表面上的半导体膜形成。

    Semiconductor element and process for manufacturing the same
    10.
    发明授权
    Semiconductor element and process for manufacturing the same 失效
    半导体元件及其制造方法

    公开(公告)号：US06818914B2

    公开(公告)日：2004-11-16

    申请号：US09994731

    申请日：2001-11-28

    申请人： Tomoyuki Ishii ,  Kazuo Yano ,  Koichi Seki ,  Toshiyuki Mine ,  Takashi Kobayashi

    发明人： Tomoyuki Ishii ,  Kazuo Yano ,  Koichi Seki ,  Toshiyuki Mine ,  Takashi Kobayashi

    IPC分类号： H01L2906

    CPC分类号： H01L29/7887 ,  H01L27/115 ,  H01L27/1203 ,  H01L29/685 ,  H01L29/7883 ,  Y10S438/962

    摘要： A semiconductor quantum memory element is disclosed which can share the terminals easily among a plurality of memory elements and can pass a high current and which is strong against noise. In order to accomplish this a control electrode is formed so as to cover the entirety of thin film regions connecting low-resistance regions. As a result, the element can have a small size and can store information with high density. Thus, a highly integrated, low power consumption non-volatile memory device can be realized with reduced size. A method of forming a memory element is also disclosed including performing the following steps of forming a first insulating layer, a second insulating layer, a first conductive layer and a layer of amorphous silicon. The amorphous silicon layer is crystallized to a polycrystalline silicon film. Semiconductor drains are deposited to form charge trapping and storage regions. A fourth insulating layer is deposited over the drains and a second conductive layer is deposited over a layer of silicon dioxide to form a control electrode of the memory element.

    摘要翻译： 公开了一种半导体量子存储器元件，其可以容易地在多个存储元件之间共享端子，并且可以通过高电流并且抵抗噪声。 为了实现这一点，形成控制电极以覆盖连接低电阻区域的整个薄膜区域。 因此，该元件可以具有小尺寸并且可以高密度地存储信息。 因此，可以以减小的尺寸实现高度集成的低功耗非易失性存储器件。 还公开了一种形成存储元件的方法，包括执行以下步骤：形成第一绝缘层，第二绝缘层，第一导电层和非晶硅层。 非晶硅层结晶成多晶硅膜。 沉积半导体漏极以形成电荷捕获和存储区域。 在漏极上沉积第四绝缘层，并且在二氧化硅层上沉积第二导电层以形成存储元件的控制电极。