公开(公告)号：US09536942B2

公开(公告)日：2017-01-03

申请号：US14363914

申请日：2012-08-02

申请人： Tsuyoshi Kawakami ,  Kenji Hamada ,  Kohei Ebihara ,  Akihiko Furukawa ,  Yuji Murakami

发明人： Tsuyoshi Kawakami ,  Kenji Hamada ,  Kohei Ebihara ,  Akihiko Furukawa ,  Yuji Murakami

IPC分类号： H01L21/266 ,  H01L29/78 ,  H01L29/872 ,  H01L29/06 ,  H01L29/861 ,  H01L29/66 ,  H01L29/08 ,  H01L29/16 ,  H01L29/423

CPC分类号： H01L29/063 ,  H01L21/266 ,  H01L29/0615 ,  H01L29/0619 ,  H01L29/0638 ,  H01L29/0692 ,  H01L29/0847 ,  H01L29/1608 ,  H01L29/42368 ,  H01L29/66136 ,  H01L29/66143 ,  H01L29/66659 ,  H01L29/7835 ,  H01L29/8611 ,  H01L29/872

摘要： A semiconductor device includes an active region formed in an upper layer portion of a semiconductor layer of a first conductivity type, and a plurality of electric field relaxation layers disposed from an edge of the active region toward the outside so as to surround the active region. The plurality of electric field relaxation layers include a plurality of first electric field relaxation layers and a plurality of second electric field relaxation layers alternately disposed adjacent to each other, the first electric field relaxation layer and the second electric field relaxation layer adjacent to each other forming a set. Impurities of a second conductivity type are implanted to the first electric field relaxation layers at a first surface density, widths of which becoming smaller as apart from the active region. Impurities of the second conductivity type are implanted to the second electric field relaxation layers at a second surface density lower than the first surface density, widths of which becoming larger as apart from the active region.

摘要翻译： 半导体器件包括形成在第一导电类型的半导体层的上层部分中的有源区和从有源区的边缘朝向外部设置以围绕有源区的多个电场弛豫层。 多个电场弛豫层包括彼此相邻交替设置的多个第一电场弛豫层和多个第二电场弛豫层，第一电场弛豫层和彼此相邻的第二电场弛豫层形成 一套。 第二导电类型的杂质以第一表面密度注入第一电场弛豫层，其宽度随着活性区域的变小而变小。 第二导电类型的杂质以比第一表面密度低的第二表面密度注入第二电场弛豫层，其宽度随着活性区域的变大而变大。

公开(公告)号：US08716717B2

公开(公告)日：2014-05-06

申请号：US13816511

申请日：2011-04-15

申请人： Tsuyoshi Kawakami ,  Akihiko Furukawa ,  Naruhisa Miura ,  Yasuhiro Kagawa ,  Kenji Hamada ,  Yoshiyuki Nakaki

发明人： Tsuyoshi Kawakami ,  Akihiko Furukawa ,  Naruhisa Miura ,  Yasuhiro Kagawa ,  Kenji Hamada ,  Yoshiyuki Nakaki

IPC分类号： H01L29/12

CPC分类号： H01L29/12 ,  H01L21/0465 ,  H01L21/265 ,  H01L21/266 ,  H01L29/0615 ,  H01L29/0619 ,  H01L29/063 ,  H01L29/0634 ,  H01L29/0692 ,  H01L29/0878 ,  H01L29/1608 ,  H01L29/6606 ,  H01L29/66068 ,  H01L29/66128 ,  H01L29/66143 ,  H01L29/66659 ,  H01L29/7835 ,  H01L29/8611 ,  H01L29/872

摘要： A RESURF layer including a plurality of P-type implantation layers having a low concentration of P-type impurity is formed adjacent to an active region. The RESURF layer includes a first RESURF layer, a second RESURF layer, a third RESURF layer, a fourth RESURF layer, and a fifth RESURF layer that are arranged sequentially from the P-type base side so as to surround the P-type base. The second RESURF layer is configured with small regions having an implantation amount equal to that of the first RESURF layer and small regions having an implantation amount equal to that of the third RESURF layer being alternately arranged in multiple. The fourth RESURF layer is configured with small regions having an implantation amount equal to that of the third RESURF layer and small regions having an implantation amount equal to that of the fifth RESURF layer being alternately arranged in multiple.

摘要翻译： 在活性区域附近形成包括具有低浓度P型杂质的多个P型注入层的RESURF层。 RESURF层包括从P型基底侧依次布置以围绕P型基底的第一RESURF层，第二RESURF层，第三RESURF层，第四RESURF层和第五RESURF层。 第二RESURF层配置有具有等于第一RESURF层的注入量的小区域，并且具有与第三RESURF层的注入量相等的注入量的小区域被交替排列成多个。 第四RESURF层配置有具有等于第三RESURF层的注入量的小区域，并且具有与第五RESURF层的注入量相等的注入量的小区域被交替排列成多个。

公开(公告)号：US09059086B2

公开(公告)日：2015-06-16

申请号：US13979564

申请日：2011-06-09

申请人： Yuji Ebiike ,  Takahiro Nakatani ,  Hiroshi Watanabe ,  Yoshio Fujii ,  Sunao Aya ,  Yoshiyuki Nakaki ,  Tsuyoshi Kawakami ,  Shuhei Nakata

发明人： Yuji Ebiike ,  Takahiro Nakatani ,  Hiroshi Watanabe ,  Yoshio Fujii ,  Sunao Aya ,  Yoshiyuki Nakaki ,  Tsuyoshi Kawakami ,  Shuhei Nakata

IPC分类号： H01L21/265 ,  H01L21/76 ,  H01L21/266 ,  H01L29/06 ,  H01L29/16 ,  H01L29/66 ,  H01L21/04 ,  H01L23/544

CPC分类号： H01L21/266 ,  H01L21/0465 ,  H01L23/544 ,  H01L29/0619 ,  H01L29/0661 ,  H01L29/1608 ,  H01L29/6606 ,  H01L29/66068 ,  H01L29/872 ,  H01L2223/54426 ,  H01L2223/54453 ,  H01L2924/0002 ,  H01L2924/00

摘要： A semiconductor device capable of suppressing generation of a high electric field and preventing a dielectric breakdown from occurring, and a method of manufacturing the same. The method of manufacturing a semiconductor device includes (a) preparing an n+ substrate to be a ground constituted by a silicon carbide semiconductor of a first conductivity type, (b) forming a recess structure surrounding an element region on the n+ substrate by using a resist pattern, and (d) forming a guard ring injection layer to be an impurity layer of a second conductivity type in a recess bottom surface and a recess side surface in the recess structure by impurity injection through the resist pattern, and a corner portion of the recess structure is covered with the impurity layer.

摘要翻译： 能够抑制高电场的产生和防止发生电介质击穿的半导体装置及其制造方法。 制造半导体器件的方法包括：（a）制备作为由第一导电类型的碳化硅半导体构成的接地的n +衬底，（b）通过使用抗蚀剂形成围绕n +衬底上的元件区域的凹陷结构 图案，以及（d）通过通过抗蚀剂图案的杂质注入，在凹部结构的凹部底面和凹部侧面中形成作为第二导电类型的杂质层的保护环注入层，以及 凹陷结构被杂质层覆盖。

公开(公告)号：US20150279931A1

公开(公告)日：2015-10-01

申请号：US14434388

申请日：2012-12-06

申请人： Ze CHEN ,  Tsuyoshi KAWAKAMI ,  Katsumi NAKAMURA

发明人： Ze Chen ,  Tsuyoshi Kawakami ,  Katsumi Nakamura

IPC分类号： H01L29/06

CPC分类号： H01L29/0619 ,  H01L29/0638 ,  H01L29/4236 ,  H01L29/7395 ,  H01L29/7397

摘要： The termination region includes a ring region (LNFLR). A plurality of ring-shaped P-type ring layers (12a˜120 are regularly arranged in the ring region (LNFLR). The ring region (LNFLR) is divided into a plurality of units which include the plurality of P-type ring layers (12a˜120 respectively. A width of each unit is constant. A total number of P-type impurities in the ring region (LNFLR) is N, the target withstand voltage is BV [V], a width of each unit is SandL [μm], and the number of the plurality of units is num, following relationships are satisfied. N≧(M×BV)γ, M=104 to 105, γ=0.55 to 1.95, SandL×num×Ecri≧2×α×BV, Ecri=2.0 to 3.0×105 [V/cm], α=100 to 101. Widths of the P-type ring layers (12a˜12f) of the plurality of units linearly decrease toward an outside of the termination region.

摘要翻译： 终端区域包括环形区域（LNFLR）。 多个环状P型环状层（12a〜120）规则地排列在环状区域（LNFLR）中，环状区域（LNFLR）被分割成多个包含多个P型环状层的单元 12a〜120，单位宽度恒定，环区（LNFLR）中P型杂质总数为N，目标耐受电压为BV [V]，各单位的宽度为SandL [μm ]，并且多个单元的数量为num，满足以下关系：N≥（M×BV）γ，M = 104〜105，γ= 0.55〜1.95，SandL×num×Ecri≥2×α×BV ，Ecri = 2.0〜3.0×105 [V / cm]，α= 100〜101.多个单元的P型环层（12a〜12f）的宽度向端子区域的外侧线性地减小。

公开(公告)号：US08183930B2

公开(公告)日：2012-05-22

申请号：US13034216

申请日：2011-02-24

申请人： Tsuyoshi Kawakami ,  Kazuyasu Nishikawa

发明人： Tsuyoshi Kawakami ,  Kazuyasu Nishikawa

IPC分类号： H03F3/68

CPC分类号： H03F3/45183 ,  H03F3/195 ,  H03F2203/45352 ,  H03F2203/45364 ,  H03F2203/45731

摘要： This invention provides a power amplifier device that satisfies both of delivering a high output and reducing the chip area occupied by the power amplifier device. The power amplifier device formed over a substrate comprises primary inductors arranged in a generally circular geometry, a ground pattern, transistor pairs, and a secondary inductor. The ground pattern is provided to extend from a portion of a region inside the circular primary inductor into regions outside the primary inductor, when viewed from the direction perpendicular to the substrate, and grounded at a plurality of points in the regions outside the primary inductor. To both ends of each primary inductor, first main electrodes of first and second transistors forming a transistor pair in linkage with the primary inductor are coupled respectively. Second main electrodes of the first and second transistors are coupled to the ground pattern in the region inside the primary inductor and have electrical conduction to the respective plurality of points grounded.

摘要翻译： 本发明提供一种功率放大器装置，其满足输出高输出和降低功率放大器装置占用的芯片面积的功能。 形成在衬底上的功率放大器器件包括以大致圆形几何形状布置的初级电感器，接地图案，晶体管对和次级电感器。 当从垂直于衬底的方向观察时，接地图案被设置成从圆形初级电感器内的区域的一部分延伸到主电感器外部的区域中，并且在初级电感器外部的区域中的多个点处接地。 在每个初级电感器的两端分别耦合形成与主电感器连接的晶体管对的第一和第二晶体管的第一主电极。 第一和第二晶体管的第二主电极在初级电感器内部的区域中耦合到接地图案，并且对相应的多个点接地进行导电。

公开(公告)号：US20140021489A1

公开(公告)日：2014-01-23

申请号：US14009628

申请日：2012-03-29

申请人： Kenji Hamada ,  Tsuyoshi Kawakami

发明人： Kenji Hamada ,  Tsuyoshi Kawakami

IPC分类号： H01L29/16

CPC分类号： H01L29/1608 ,  H01L21/046 ,  H01L29/0615 ,  H01L29/0619 ,  H01L29/0878 ,  H01L29/66128 ,  H01L29/66136 ,  H01L29/7395 ,  H01L29/7811 ,  H01L29/8611 ,  H01L29/872

摘要： A semiconductor device having a high withstand voltage in which a stable withstand voltage can be obtained and a method for manufacturing the same. A JTE region having a second conductivity type is formed in a portion on an outer peripheral end side of an SiC substrate from a second conductivity type SiC region in a vicinal portion of a surface on one of sides in a thickness direction of a first conductivity type SiC epitaxial layer. A first conductivity type SiC region having a higher concentration of an impurity having the first conductivity type than that of the SiC epitaxial layer is formed in at least a vicinal portion of a surface on one of sides in a thickness direction of a portion in which the JTE regions are bonded to each other.

摘要翻译： 具有能够获得稳定耐受电压的高耐受电压的半导体器件及其制造方法。 具有第二导电类型的JTE区域形成在SiC衬底的外周端侧的从第一导电类型的厚度方向的一侧的表面的相邻部分中的第二导电型SiC区域的部分中 SiC外延层。 在第一导电类型的SiC区域中，具有比SiC外延层的第一导电类型的杂质浓度高的第一导电型SiC区域在至少一个侧面中的一个侧面的连续部分上形成， JTE地区相互结合。

公开(公告)号：US08416022B2

公开(公告)日：2013-04-09

申请号：US13450184

申请日：2012-04-18

申请人： Tsuyoshi Kawakami ,  Kazuyasu Nishikawa

发明人： Tsuyoshi Kawakami ,  Kazuyasu Nishikawa

IPC分类号： H03F3/68

CPC分类号： H03F3/45183 ,  H03F3/195 ,  H03F2203/45352 ,  H03F2203/45364 ,  H03F2203/45731

摘要： A power amplifier device that satisfies both delivering a high output and reducing the chip area occupied by the power amplifier device. Over a substrate, are primary inductors arranged in a generally circular geometry, a ground pattern, transistor pairs, and a secondary inductor. The ground pattern extends from a portion of a region inside the circular primary inductor into regions outside the primary inductor, and grounded at a plurality of points in the regions outside the primary inductor. The primary inductors are coupled to the ground pattern through transistors.

摘要翻译： 一种功率放大器装置，其满足输出高输出并减小功率放大器装置占用的芯片面积。 在基板上，是以大致圆形几何形状布置的初级电感器，接地图案，晶体管对和次级电感器。 接地图案从圆形初级电感器内的区域的一部分延伸到初级电感器外部的区域中，并且在初级电感器外部的区域中的多个点处接地。 主电感器通过晶体管耦合到接地图案。

公开(公告)号：US09385183B2

公开(公告)日：2016-07-05

申请号：US14434388

申请日：2012-12-06

申请人： Ze Chen ,  Tsuyoshi Kawakami ,  Katsumi Nakamura

发明人： Ze Chen ,  Tsuyoshi Kawakami ,  Katsumi Nakamura

IPC分类号： H01L27/01 ,  H01L27/12 ,  H01L31/0392 ,  H01L29/06 ,  H01L29/739 ,  H01L29/423

CPC分类号： H01L29/0619 ,  H01L29/0638 ,  H01L29/4236 ,  H01L29/7395 ,  H01L29/7397

摘要： The termination region includes a ring region (LNFLR). A plurality of ring-shaped P-type ring layers are regularly arranged in the ring region (LNFLR). The ring region (LNFLR) is divided into a plurality of units which include the plurality of P-type ring layers respectively. A width of each unit is constant. A total number of P-type impurities in the ring region (LNFLR) is N, the target withstand voltage is BV [V], a width of each unit is SandL [μm], and the number of the plurality of units is num, following relationships are satisfied. N≧(M×BV)γ, M=104 to 105, γ=0.55 to 1.95, SandL×num×Ecri≧2×α×BV, Ecri=2.0 to 3.0×105 [V/cm], α=100 to 101. Widths of the P-type ring layers of the plurality of units linearly decrease toward an outside of the termination region.

摘要翻译： 终端区域包括环形区域（LNFLR）。 多个环形P型环层规则地布置在环形区域（LNFLR）中。 环区域（LNFLR）被分成多个单元，分别包括多个P型环层。 每个单位的宽度是恒定的。 环状区域（LNFLR）中的P型杂质的总数为N，目标耐受电压为BV [V]，每个单位的宽度为SandL [μm]，多个单位的数量为num， 满足以下关系。 N≥（M×BV）γ，M = 104〜105，γ= 0.55〜1.95，SandL×num×Ecri≥2×α×BV，Ecri = 2.0〜3.0×105 [V / cm]，α= 多个单元的P型环层的宽度朝着端接区域的外侧线性地减小。

公开(公告)号：US08866158B2

公开(公告)日：2014-10-21

申请号：US14009628

申请日：2012-03-29

申请人： Kenji Hamada ,  Tsuyoshi Kawakami

发明人： Kenji Hamada ,  Tsuyoshi Kawakami

IPC分类号： H01L29/15 ,  H01L29/16 ,  H01L21/04 ,  H01L29/66 ,  H01L29/06 ,  H01L29/861 ,  H01L29/739 ,  H01L29/78 ,  H01L29/08 ,  H01L29/872

CPC分类号： H01L29/1608 ,  H01L21/046 ,  H01L29/0615 ,  H01L29/0619 ,  H01L29/0878 ,  H01L29/66128 ,  H01L29/66136 ,  H01L29/7395 ,  H01L29/7811 ,  H01L29/8611 ,  H01L29/872

摘要： A semiconductor device having a high withstand voltage in which a stable withstand voltage can be obtained and a method for manufacturing the same. A JTE region having a second conductivity type is formed in a port ion on an outer peripheral end side of an SiC substrate from a second conductivity type SiC region in a vicinal portion of a surface on one of sides in a thickness direction of a first conductivity type SiC epitaxial layer. A first conductivity type SiC region having a higher concentration of an impurity having the first conductivity type than that of the SiC epitaxial layer is formed in at least a vicinal portion of a surface on one of sides in a thickness direction of a portion in which the JTE regions are bonded to each other.

摘要翻译： 具有能够获得稳定耐受电压的高耐受电压的半导体器件及其制造方法。 具有第二导电类型的JTE区域形成在SiC衬底的外周端侧上的端口离子中，该第二导电型SiC区域在第一导电性的厚度方向的一侧的表面的邻近部分中 型SiC外延层。 在第一导电类型的SiC区域中，具有比SiC外延层的第一导电类型的杂质浓度高的第一导电型SiC区域在至少一个侧面中的一个侧面的连续部分上形成， JTE地区相互结合。

公开(公告)号：US20130288467A1

公开(公告)日：2013-10-31

申请号：US13979564

申请日：2011-06-09

申请人： Yuji Ebiike ,  Takahiro Nakatani ,  Hiroshi Watanabe ,  Yoshio Fujii ,  Sunao Aya ,  Yoshiyuki Nakaki ,  Tsuyoshi Kawakami ,  Shuhei Nakata

发明人： Yuji Ebiike ,  Takahiro Nakatani ,  Hiroshi Watanabe ,  Yoshio Fujii ,  Sunao Aya ,  Yoshiyuki Nakaki ,  Tsuyoshi Kawakami ,  Shuhei Nakata

IPC分类号： H01L21/266

CPC分类号： H01L21/266 ,  H01L21/0465 ,  H01L23/544 ,  H01L29/0619 ,  H01L29/0661 ,  H01L29/1608 ,  H01L29/6606 ,  H01L29/66068 ,  H01L29/872 ,  H01L2223/54426 ,  H01L2223/54453 ,  H01L2924/0002 ,  H01L2924/00

摘要： A semiconductor device capable of suppressing generation of a high electric field and preventing a dielectric breakdown from occurring, and a method of manufacturing the same. The method of manufacturing a semiconductor device includes (a) preparing an n+ substrate to be a ground constituted by a silicon carbide semiconductor of a first conductivity type, (b) forming a recess structure surrounding an element region on the n+ substrate by using a resist pattern, and (c) forming a guard ring injection layer to be an impurity layer of a second conductivity type in a recess bottom surface and a recess side surface in the recess structure by impurity injection through the resist pattern, and a corner portion of the recess structure is covered with the impurity layer.

摘要翻译： 能够抑制高电场的产生和防止发生电介质击穿的半导体装置及其制造方法。 制造半导体器件的方法包括：（a）制备作为由第一导电类型的碳化硅半导体构成的接地的n +衬底，（b）通过使用抗蚀剂形成围绕n +衬底上的元件区域的凹陷结构 图案，以及（c）通过通过抗蚀剂图案的杂质注入，在凹陷结构的凹槽底表面和凹陷侧表面中形成作为第二导电类型的杂质层的保护环注入层，以及 凹陷结构被杂质层覆盖。