公开(公告)号：US09847398B1

公开(公告)日：2017-12-19

申请号：US15208616

申请日：2016-07-13

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Yu-Hsiang Hung ,  Chih-Kai Hsu ,  Ssu-I Fu ,  Wei-Chi Cheng ,  Jyh-Shyang Jenq

IPC: H01L29/423 ,  H01L23/528 ,  H01L21/768 ,  H01L29/66

CPC classification number: H01L29/42364 ,  H01L21/76897 ,  H01L23/485 ,  H01L29/66545 ,  H01L29/785

Abstract: A semiconductor device is disclosed. The semiconductor device includes: a substrate; a gate structure on the substrate; a spacer around the gate structure; a contact etch stop layer (CESL) on the spacer; an interlayer dielectric (ILD) layer adjacent to one side of the gate structure and contacting the CESL; and a contact plug adjacent to another side of the gate structure and contacting the CESL.

公开(公告)号：US20170294508A1

公开(公告)日：2017-10-12

申请号：US15144842

申请日：2016-05-03

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Chih-Kai Hsu ,  Ssu-I Fu ,  Yu-Hsiang Hung ,  Wei-Chi Cheng ,  Jyh-Shyang Jenq ,  Tsung-Mu Yang

IPC: H01L29/06 ,  H01L21/768 ,  H01L23/535 ,  H01L29/78 ,  H01L29/66

CPC classification number: H01L29/0653 ,  H01L21/28518 ,  H01L21/76805 ,  H01L21/76843 ,  H01L21/76855 ,  H01L21/76895 ,  H01L23/485 ,  H01L23/535 ,  H01L29/66795 ,  H01L29/785

Abstract: A method for fabricating semiconductor device is disclosed. First, a substrate is provided, and a gate structure is formed on the substrate. Next, a recess is formed adjacent to two sides of the gate structure, and an epitaxial layer is formed in the recess, in which a top surface of the epitaxial layer is lower than a top surface of the substrate. Next, a cap layer is formed on the epitaxial layer, in which a top surface of the cap layer is higher than a top surface of the substrate.

公开(公告)号：US09685385B1

公开(公告)日：2017-06-20

申请号：US15226929

申请日：2016-08-03

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Yu-Hsiang Hung ,  Ssu-I Fu ,  Chih-Kai Hsu ,  Wei-Chi Cheng ,  Jyh-Shyang Jenq

IPC: H01L21/768 ,  H01L21/8238 ,  H01L21/311 ,  H01L21/306 ,  H01L21/02 ,  H01L29/66 ,  H01L21/762 ,  H01L29/06 ,  H01L21/265

CPC classification number: H01L21/823821 ,  H01L21/02164 ,  H01L21/0217 ,  H01L21/02636 ,  H01L21/26513 ,  H01L21/30604 ,  H01L21/31111 ,  H01L21/31144 ,  H01L21/76224 ,  H01L21/823814 ,  H01L21/823828 ,  H01L21/823871 ,  H01L21/823878 ,  H01L29/0653 ,  H01L29/66636 ,  H01L29/66795

Abstract: The present invention provides a method for forming a semiconductor device, including the following steps: first, a substrate is provided, at least one gate is formed on the substrate, a contact etching stop layer (CESL) and a first dielectric layer are formed on the substrate in sequence, afterwards, a first etching process is performed to remove the first dielectric layer, and to expose a top surface and at least one sidewall of the etching stop layer, next, a second etching process is performed to partially remove the contact etching stop layer, and to form at least one epitaxial recess in the substrate. Afterwards, an epitaxial process is performed, to form an epitaxial layer in the epitaxial recess, and a contact structure is then formed on the epitaxial layer.

公开(公告)号：US20160358827A1

公开(公告)日：2016-12-08

申请号：US15241077

申请日：2016-08-19

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Chih-Kai Hsu ,  Ssu-I Fu ,  Yu-Hsiang Hung ,  Wei-Chi Cheng ,  Jyh-Shyang Jenq

IPC: H01L21/84 ,  H01L21/306 ,  H01L21/02 ,  H01L21/311 ,  H01L29/66 ,  H01L21/762 ,  H01L21/308

CPC classification number: H01L21/845 ,  H01L21/02238 ,  H01L21/02365 ,  H01L21/02367 ,  H01L21/762 ,  H01L21/76202 ,  H01L21/7624 ,  H01L27/1211 ,  H01L29/0649 ,  H01L29/0653 ,  H01L29/1054 ,  H01L29/66795 ,  H01L29/785

Abstract: A method of forming a fin-shaped structure includes the following step. A substrate having a first area and a second area is provided. An epitaxial structure is formed in the first area. An epitaxial structure is formed in the second area after the epitaxial structure in the first area is formed, wherein the surface area of the epitaxial structure in the first area is different from the surface area of the epitaxial structure in the second area.

Abstract translation: 形成翅片状结构的方法包括以下步骤。 提供具有第一区域和第二区域的衬底。 在第一区域中形成外延结构。 在形成第一区域中的外延结构之后，在第二区域中形成外延结构，其中第一区域中的外延结构的表面积与第二区域中的外延结构的表面积不同。

公开(公告)号：US11948975B2

公开(公告)日：2024-04-02

申请号：US17509061

申请日：2021-10-24

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Chih-Kai Hsu ,  Ssu-I Fu ,  Yu-Hsiang Hung ,  Wei-Chi Cheng ,  Jyh-Shyang Jenq

IPC: H01L29/08 ,  H01L21/8238 ,  H01L27/092 ,  H01L29/423 ,  H01L29/66 ,  H01L29/78

CPC classification number: H01L29/0847 ,  H01L21/823821 ,  H01L27/0924 ,  H01L29/42356 ,  H01L29/42368 ,  H01L29/66545 ,  H01L29/66636 ,  H01L29/66795 ,  H01L29/78 ,  H01L29/7833 ,  H01L29/7848 ,  H01L29/785 ,  H01L29/665

Abstract: A method for fabricating semiconductor device includes the steps of: forming a gate structure on a substrate; forming a spacer around the gate structure; and forming a buffer layer adjacent to the gate structure. Preferably, the buffer layer includes a crescent moon shape and the buffer layer includes an inner curve, an outer curve, and a planar surface connecting the inner curve and an outer curve along a top surface of the substrate, in which the planar surface directly contacts the outer curve on an outer sidewall of the spacer.

公开(公告)号：US10566285B2

公开(公告)日：2020-02-18

申请号：US15170954

申请日：2016-06-02

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Chih-Kai Hsu ,  Yu-Hsiang Hung ,  Wei-Chi Cheng ,  Ssu-I Fu ,  Jyh-Shyang Jenq

IPC: H01L23/535 ,  H01L29/267 ,  H01L29/24 ,  H01L29/165 ,  H01L29/161 ,  H01L29/08 ,  H01L23/528 ,  H01L21/768 ,  H01L29/78 ,  H01L23/485

Abstract: A method for fabricating semiconductor device is disclosed. The method includes the steps of: providing a substrate; forming a gate structure on the substrate; forming an epitaxial layer adjacent to the gate structure; forming an interlayer dielectric (ILD) layer on the gate structure; forming a first contact hole in the ILD layer adjacent to the gate structure; and forming a cap layer in the recess, in which a top surface of the cap layer is even with or lower than a top surface of the substrate.

公开(公告)号：US10541304B2

公开(公告)日：2020-01-21

申请号：US15983077

申请日：2018-05-17

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Chih-Kai Hsu ,  Ssu-I Fu ,  Yu-Hsiang Hung ,  Wei-Chi Cheng ,  Jyh-Shyang Jenq

IPC: H01L29/08 ,  H01L29/78 ,  H01L21/8238 ,  H01L29/66 ,  H01L27/092 ,  H01L29/423

Abstract: A method for fabricating semiconductor device includes the steps of: providing a substrate; forming a gate structure on the substrate; forming a spacer adjacent to the gate structure; forming a recess adjacent to the spacer; forming a buffer layer in the recess, wherein the buffer layer comprises a crescent moon shape; and forming an epitaxial layer on the buffer layer.

公开(公告)号：US20180269288A1

公开(公告)日：2018-09-20

申请号：US15983077

申请日：2018-05-17

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Chih-Kai Hsu ,  Ssu-I Fu ,  Yu-Hsiang Hung ,  Wei-Chi Cheng ,  Jyh-Shyang Jenq

IPC: H01L29/08 ,  H01L29/78 ,  H01L29/66 ,  H01L29/423

Abstract: A method for fabricating semiconductor device includes the steps of: providing a substrate; forming a gate structure on the substrate; forming a spacer adjacent to the gate structure; forming a recess adjacent to the spacer; forming a buffer layer in the recess, wherein the buffer layer comprises a crescent moon shape; and forming an epitaxial layer on the buffer layer.

公开(公告)号：US10008569B2

公开(公告)日：2018-06-26

申请号：US15259060

申请日：2016-09-08

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Chih-Kai Hsu ,  Ssu-I Fu ,  Yu-Hsiang Hung ,  Wei-Chi Cheng ,  Jyh-Shyang Jenq

IPC: H01L29/08 ,  H01L29/423 ,  H01L29/66 ,  H01L29/78

CPC classification number: H01L29/0847 ,  H01L29/42356 ,  H01L29/42368 ,  H01L29/665 ,  H01L29/66545 ,  H01L29/66636 ,  H01L29/78 ,  H01L29/7833 ,  H01L29/7848 ,  H01L29/785

Abstract: A method for fabricating semiconductor device is disclosed. First, a substrate is provided, a gate structure is formed on the substrate, a recess is formed adjacent to the gate structure, a buffer layer is formed in the recess, and an epitaxial layer is formed on the buffer layer. Preferably, the buffer layer includes a crescent moon shape.

公开(公告)号：US09735047B1

公开(公告)日：2017-08-15

申请号：US15172161

申请日：2016-06-03

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Ching-Yu Chang ,  Ssu-I Fu ,  Yu-Hsiang Hung ,  Chih-Kai Hsu ,  Wei-Chi Cheng ,  Jyh-Shyang Jenq

IPC: H01L21/336 ,  H01L21/768 ,  H01L29/66 ,  H01L29/423 ,  H01L21/02 ,  H01L21/311 ,  H01L23/532 ,  H01L21/8234 ,  H01L27/088 ,  H01L21/28 ,  H01L21/8238

CPC classification number: H01L21/7682 ,  H01L21/02164 ,  H01L21/02274 ,  H01L21/0228 ,  H01L21/28132 ,  H01L21/28141 ,  H01L21/2815 ,  H01L21/28247 ,  H01L21/31105 ,  H01L21/823431 ,  H01L21/823456 ,  H01L21/823462 ,  H01L21/823468 ,  H01L21/823864 ,  H01L23/485 ,  H01L27/0886 ,  H01L29/42364 ,  H01L29/6653 ,  H01L29/6656 ,  H01L29/66689 ,  H01L29/66719

Abstract: A semiconductor device includes: a substrate, a gate structure on the substrate, and a spacer adjacent to the gate structure, in which the spacer extends to a top surface of the gate structure, a top surface of the spacer includes a planar surface, the spacer encloses an air gap, and the spacer is composed of a single material. The gate structure includes a high-k dielectric layer, a work function metal layer, and a low resistance metal layer, in which the high-k dielectric layer is U-shaped. The semiconductor device also includes an interlayer dielectric (ILD) layer around the gate structure and a hard mask on the spacer, in which the top surface of the hard mask is even with the top surface of the ILD layer.