公开(公告)号：US20140361438A1

公开(公告)日：2014-12-11

申请号：US13911062

申请日：2013-06-05

Applicant: United Microelectronics Corp.

Inventor： Fan-Qing Zeng ,  Ching Hwa Tey ,  Xiaoqing Xu

IPC: H01L23/58 ,  H01L21/768

CPC classification number: H01L23/585 ,  H01L23/564 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A method of forming a seal ring structure includes the following steps. A substrate is provided, and the substrate includes a seal ring region. A metal stack is formed in the seal ring region. A first dielectric layer covering the metal stack is formed. A part of the first dielectric layer is removed to form an opening to expose the metal stack, and at least a side of the opening is not perpendicular to a top surface of the first dielectric layer. A conductive layer is formed to fill the opening. A second dielectric layer is formed to continuously cover the first dielectric layer and the conductive layer, and the second dielectric layer has a v-shaped surface totally overlapping the conductive layer.

Abstract translation: 形成密封环结构的方法包括以下步骤。 提供基板，并且基板包括密封环区域。 在密封圈区域中形成金属叠层。 形成覆盖金属叠层的第一介电层。 去除第一电介质层的一部分以形成露出金属叠层的开口，并且开口的至少一侧不垂直于第一电介质层的顶表面。 形成导电层以填充开口。 形成第二电介质层以连续地覆盖第一电介质层和导电层，并且第二介电层具有与导电层完全重叠的V形表面。

公开(公告)号：US20240332067A1

公开(公告)日：2024-10-03

申请号：US18739344

申请日：2024-06-11

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Yunfei Li ,  Ji Feng ,  Guohai Zhang ,  Ching Hwa Tey

IPC: H01L21/768 ,  H01L21/02 ,  H01L23/532 ,  H01L23/535

CPC classification number: H01L21/7682 ,  H01L21/02063 ,  H01L21/76805 ,  H01L21/76814 ,  H01L21/76895 ,  H01L23/5329 ,  H01L23/535

Abstract: A transistor structure with an air gap includes a substrate. A transistor is disposed on the substrate. An etching stop layer covers and contacts the transistor and the substrate. A first dielectric layer covers and contacts the etching stop layer. A second dielectric layer covers the first dielectric layer. A trench is disposed on the gate structure and within the first dielectric layer and the second dielectric layer. A width of the trench within the second dielectric layer is smaller than a width of the trench within the first dielectric layer. A filling layer is disposed within the trench and covers the top surface of the second dielectric layer. An air gap is formed within the filling layer.

公开(公告)号：US12094896B2

公开(公告)日：2024-09-17

申请号：US17984261

申请日：2022-11-10

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Zhaoyao Zhan ,  Qianwei Ding ,  Xiaohong Jiang ,  Ching Hwa Tey

IPC: H01L27/146

CPC classification number: H01L27/1461 ,  H01L27/14623

Abstract: A photosensitive device is disclosed, including an integrated circuit structure, a first pad and a second pad exposed from a surface of the integrated circuit structure, a first material layer disposed on the surface of the integrated circuit structure and covering the first pad, and a second material layer disposed on the first material layer and covering the second pad. The first material layer and the second material layer form a heterojunction photodiode.

公开(公告)号：US11641000B2

公开(公告)日：2023-05-02

申请号：US17137300

申请日：2020-12-29

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Zhaoyao Zhan ,  Qianwei Ding ,  Xiaohong Jiang ,  Ching Hwa Tey

IPC: H01L31/032 ,  H01L27/146 ,  H01L31/028 ,  H01L31/0352

Abstract: The invention provides an image sensor, the image sensor includes a substrate, a first circuit layer located on the substrate, and at least one nanowire photodiode located on the first circuit layer and electrically connected to the first circuit layer, the nanowire photodiode comprises a lower material layer and an upper material layer with a P-N junction between the lower material layer and the upper material layer, the lower material layer includes perovskite material.

公开(公告)号：US11127621B2

公开(公告)日：2021-09-21

申请号：US16673929

申请日：2019-11-04

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Ji Feng ,  Yunfei Li ,  Guohai Zhang ,  Ching Hwa Tey ,  Jingling Wang

IPC: H01L21/762 ,  H01L21/76 ,  H01L21/311 ,  H01L21/265

Abstract: A method of forming a semiconductor device includes following steps. Firstly, a substrate is provided and the substrate has a first semiconductor layer formed thereon. Next, an isolating structure is formed in the first semiconductor layer, and a sacrificial layer is formed on the first semiconductor layer by consuming a top portion of the first semiconductor layer. Then, the sacrificial layer is removed to form a second semiconductor layer, and a portion of the isolating structure is also removed to form a shallow trench isolation (STI), with a top surface of the shallow trench isolation being substantially coplanar with a top surface of the second semiconductor layer.

公开(公告)号：US10909299B1

公开(公告)日：2021-02-02

申请号：US16881020

申请日：2020-05-22

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Wei Pang ,  Jing Feng ,  Xiaohong Jiang ,  Ching Hwa Tey

IPC: G06F17/50 ,  G03F1/36 ,  G06F30/392 ,  G06F119/06 ,  G06F30/373 ,  G06F30/337 ,  G06F30/347

Abstract: A method for stabilizing bandgap voltage includes the steps of: providing a first layout pattern designated with a first voltage; reducing a critical dimension of the first layout pattern for generating a second layout pattern corresponding to a second voltage; matching the second voltage with a target voltage; and then outputting the second layout pattern to a mask. Preferably, the first layout pattern and the second layout pattern include polysilicon resistor patterns.

公开(公告)号：US09685387B1

公开(公告)日：2017-06-20

申请号：US15185014

申请日：2016-06-16

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Zhe Wang ,  Ching Hwa Tey ,  Lu Zou

IPC: H01L23/58 ,  H01L21/66 ,  H01L27/092 ,  H01L29/06 ,  H01L21/8238 ,  G01R31/26 ,  G01R31/28

CPC classification number: H01L22/34 ,  G01R31/2884 ,  H01L21/823878 ,  H01L21/823892 ,  H01L22/30 ,  H01L27/092 ,  H01L27/0928 ,  H01L29/0653

Abstract: A test key and a method for checking the window of a doped region using the test key are provided in the present invention. The test key includes a P-type first well region on a substrate, a P-type substrate region adjacent to the first well region, a N-type first doped region partially overlapping the first well region, two P-type second doped regions at two opposite sides of the first well region, a N-type second well region surrounding the first doped region, the substrate region and the two second doped regions, and a plurality of test pads above the above-identified region.

公开(公告)号：US09305887B2

公开(公告)日：2016-04-05

申请号：US13911062

申请日：2013-06-05

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Fan-Qing Zeng ,  Ching Hwa Tey ,  Xiaoqing Xu

IPC: H01L23/58 ,  H01L23/00

CPC classification number: H01L23/585 ,  H01L23/564 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A method of forming a seal ring structure includes the following steps. A substrate is provided, and the substrate includes a seal ring region. A metal stack is formed in the seal ring region. A first dielectric layer covering the metal stack is formed. A part of the first dielectric layer is removed to form an opening to expose the metal stack, and at least a side of the opening is not perpendicular to a top surface of the first dielectric layer. A conductive layer is formed to fill the opening. A second dielectric layer is formed to continuously cover the first dielectric layer and the conductive layer, and the second dielectric layer has a v-shaped surface totally overlapping the conductive layer.

Abstract translation: 形成密封环结构的方法包括以下步骤。 提供基板，并且基板包括密封环区域。 在密封圈区域中形成金属叠层。 形成覆盖金属叠层的第一介电层。 去除第一电介质层的一部分以形成露出金属叠层的开口，并且开口的至少一侧不垂直于第一电介质层的顶表面。 形成导电层以填充开口。 形成第二电介质层以连续地覆盖第一电介质层和导电层，并且第二电介质层具有与导电层完全重叠的V形表面。