公开(公告)号：US11527561B2

公开(公告)日：2022-12-13

申请号：US16931400

申请日：2020-07-16

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Zhaoyao Zhan ,  Qianwei Ding ,  Xiaohong Jiang ,  Ching Hwa Tey

IPC: H01L27/146

Abstract: A photosensitive device is disclosed, including an integrated circuit structure, a first pad and a second pad exposed from a surface of the integrated circuit structure, a first material layer disposed on the surface of the integrated circuit structure and covering the first pad, and a second material layer disposed on the first material layer and covering the second pad. The first material layer and the second material layer form a photodiode.

公开(公告)号：US09941161B2

公开(公告)日：2018-04-10

申请号：US14838374

申请日：2015-08-28

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Duan Quan Liao ,  Yikun Chen ,  Ching Hwa Tey

IPC: H01L21/768 ,  H01L21/306 ,  H01L29/78 ,  H01L29/66 ,  H01L21/3105 ,  H01L21/283

CPC classification number: H01L21/76897 ,  H01L21/283 ,  H01L21/30625 ,  H01L21/31051 ,  H01L21/76829 ,  H01L29/6653 ,  H01L29/66545 ,  H01L29/78 ,  H01L29/785

Abstract: A method for fabricating semiconductor device is disclosed. The method includes the steps of: providing a substrate having a gate structure thereon, a first hard mask atop the gate structure, and an interlayer dielectric (ILD) layer around the gate structure and the first hard mask; removing part of the first hard mask; forming a second hard mask layer on the first hard mask and the ILD layer; and planarizing part of the second hard mask layer to form a second hard mask on the first hard mask.

公开(公告)号：US09276057B2

公开(公告)日：2016-03-01

申请号：US14165535

申请日：2014-01-27

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Duan Quan Liao ,  Yikun Chen ,  Ching Hwa Tey ,  Xiao Zhong Zhu

IPC: H01L29/94 ,  H01L49/02 ,  H01L21/768 ,  H01L23/522 ,  H01L23/532 ,  H01L27/108

CPC classification number: H01L28/75 ,  H01L21/76807 ,  H01L23/5223 ,  H01L23/53238 ,  H01L23/5329 ,  H01L23/53295 ,  H01L27/10808 ,  H01L27/10852 ,  H01L28/91 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A capacitor structure includes a substrate with a plurality of dielectric layers sequentially formed thereon, a trench formed in the dielectric layers, wherein the trench is composed of at least two interconnected dual damascene recesses, each dual damascene recess formed in one dielectric layer; and a capacitor multilayer disposed on the sidewall of the trench.

Abstract translation: 电容器结构包括其上顺序地形成有多个电介质层的衬底，形成在电介质层中的沟槽，其中沟槽由至少两个互连的双镶嵌凹部组成，每个双镶嵌凹部形成在一个介电层中; 以及设置在沟槽的侧壁上的电容器多层。

公开(公告)号：US11355389B2

公开(公告)日：2022-06-07

申请号：US17133652

申请日：2020-12-24

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Yunfei Li ,  Ji Feng ,  Guohai Zhang ,  Ching Hwa Tey

IPC: H01L21/768 ,  H01L23/535 ,  H01L23/532 ,  H01L21/02

Abstract: A transistor structure with an air gap includes a substrate. A transistor is disposed on the substrate. An etching stop layer covers and contacts the transistor and the substrate. A first dielectric layer covers and contacts the etching stop layer. A second dielectric layer covers the first dielectric layer. A trench is disposed on the gate structure and within the first dielectric layer and the second dielectric layer. A width of the trench within the second dielectric layer is smaller than a width of the trench within the first dielectric layer. A filling layer is disposed within the trench and covers the top surface of the second dielectric layer. An air gap is formed within the filling layer.

公开(公告)号：US11101361B1

公开(公告)日：2021-08-24

申请号：US16886744

申请日：2020-05-28

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Zhaoyao Zhan ,  Qianwei Ding ,  Xiaohong Jiang ,  Ching Hwa Tey

IPC: H01L29/423 ,  H01L29/06 ,  H01L29/417 ,  H01L29/786 ,  H01L21/02 ,  H01L21/762 ,  H01L29/66 ,  H01L29/76 ,  H01L29/16 ,  H01L29/24

Abstract: A GAA transistor includes a semiconductor substrate. A first shallow trench isolation (STI) is embedded in the semiconductor substrate. A top surface of the first STI is lower than a top surface of the semiconductor substrate. A nanowire crosses the first STI and is disposed on the first STI. A gate structure contacts and wraps around the nanowire. A source electrode contacts a first end of the nanowire. A drain electrode contacts a second end of the nanowire.

公开(公告)号：US09583594B2

公开(公告)日：2017-02-28

申请号：US14829649

申请日：2015-08-19

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Duan Quan Liao ,  Yikun Chen ,  Ching Hwa Tey

IPC: H01L23/535 ,  H01L29/66 ,  H01L21/768 ,  H01L29/06

CPC classification number: H01L21/0337 ,  H01L21/3086 ,  H01L21/31144 ,  H01L21/76816 ,  H01L29/0657 ,  H01L29/66553

Abstract: A semiconductor device and a method of fabricating the same, the semiconductor device includes a hard mask layer and a plurality of spacers. The hard mask layer is disposed on a target layer and has a first material and a second material. The spacers are disposed on the hard mask layer, wherein a first portion of the spacers is disposed on the first material, and a second portion of the spacers is disposed on the second material.

Abstract translation: 半导体器件及其制造方法，半导体器件包括硬掩模层和多个间隔物。 硬掩模层设置在目标层上并具有第一材料和第二材料。 间隔物设置在硬掩模层上，其中间隔物的第一部分设置在第一材料上，间隔物的第二部分设置在第二材料上。

公开(公告)号：US12080734B2

公开(公告)日：2024-09-03

申请号：US17984243

申请日：2022-11-10

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Zhaoyao Zhan ,  Qianwei Ding ,  Xiaohong Jiang ,  Ching Hwa Tey

IPC: H01L27/146

CPC classification number: H01L27/1461 ,  H01L27/14623

Abstract: A method for forming a photosensitive device includes the steps of providing an integrated circuit structure having a first pad and a second pad exposed from a surface of the integrated circuit structure, forming a first material layer on the surface of the integrated circuit structure, patterning the first material layer to expose the second pad, forming a second material layer on the first material layer and covering the second pad, and patterning the second material.

公开(公告)号：US12040224B2

公开(公告)日：2024-07-16

申请号：US17737011

申请日：2022-05-04

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Yunfei Li ,  Ji Feng ,  Guohai Zhang ,  Ching Hwa Tey

IPC: H01L21/768 ,  H01L21/02 ,  H01L23/532 ,  H01L23/535

CPC classification number: H01L21/7682 ,  H01L21/02063 ,  H01L21/76805 ,  H01L21/76814 ,  H01L21/76895 ,  H01L23/5329 ,  H01L23/535

Abstract: A transistor structure with an air gap includes a substrate. A transistor is disposed on the substrate. An etching stop layer covers and contacts the transistor and the substrate. A first dielectric layer covers and contacts the etching stop layer. A second dielectric layer covers the first dielectric layer. A trench is disposed on the gate structure and within the first dielectric layer and the second dielectric layer. A width of the trench within the second dielectric layer is smaller than a width of the trench within the first dielectric layer. A filling layer is disposed within the trench and covers the top surface of the second dielectric layer. An air gap is formed within the filling layer.

公开(公告)号：US09401280B2

公开(公告)日：2016-07-26

申请号：US14288399

申请日：2014-05-28

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Duan Quan Liao ,  Wei Cheng ,  Yikun Chen ,  Ching Hwa Tey ,  Xiao Zhong Zhu

IPC: H01L21/28 ,  H01L27/115

CPC classification number: H01L21/28273 ,  H01L27/11521 ,  H01L27/11534

Abstract: A semiconductor process includes the following steps. A first gate is formed on a substrate, wherein the first gate includes a stacked gate on the substrate and a cap on the stacked gate. A spacer material is formed to conformally cover the first gate and the substrate. The spacer material is etched to form a spacer on a side of the first gate and a block on the other side of the first gate corresponding to the side. A material covers the substrate, the block, the first gate and the spacer, wherein the top surface of the material is a flat surface. The block, the spacer and the material are pulled down with the same pulling selectivity so that an assisting gate is formed from the block and a selective gate is formed from the spacer.

Abstract translation: 半导体工艺包括以下步骤。 第一栅极形成在衬底上，其中第一栅极包括衬底上的堆叠栅极和堆叠栅极上的帽。 形成间隔物材料以保形地覆盖第一栅极和衬底。 蚀刻间隔材料以在第一栅极的一侧上形成间隔物，并且在第一栅极的另一侧上对应于侧面的块。 材料覆盖基板，块，第一栅极和间隔件，其中材料的顶表面是平坦的表面。 块，间隔物和材料以相同的拉拔选择性被拉下，使得从块形成辅助栅极，并且由间隔物形成选择栅极。

公开(公告)号：US09023726B1

公开(公告)日：2015-05-05

申请号：US14082200

申请日：2013-11-18

Applicant: United Microelectronics Corp.

Inventor： Wei Cheng ,  Ming Sheng Xu ,  Duan Quan Liao ,  Yikun Chen ,  Ching Hwa Tey

IPC: H01L21/3205 ,  H01L21/28 ,  H01L21/8234

CPC classification number: H01L21/28132 ,  H01L21/28273 ,  H01L21/823468 ,  H01L27/11524

Abstract: A method of fabricating a semiconductor device includes the following steps. At least a first gate stack layer and at least a second gate stack layer protruding from a conductive layer on a substrate are provided. Subsequently, two spacers and a protective layer are formed on the conductive layer, and the two spacers and the protective layer jointly surround the protruded first gate stack layer and the protruded second gate stack layer. The two spacers and the protective layer are used as a mask to remove a part of the conductive layer. Afterwards, the two spacers and the protective layer are removed.

Abstract translation: 制造半导体器件的方法包括以下步骤。 提供至少一个第一栅堆叠层和至少一个从衬底上的导电层突出的第二栅堆叠层。 随后，在导电层上形成两个间隔物和保护层，两个间隔物和保护层共同围绕突出的第一栅叠层和突出的第二栅堆叠层。 将两个间隔物和保护层用作掩模以去除导电层的一部分。 之后，取下两个间隔物和保护层。