公开(公告)号：US09964866B2

公开(公告)日：2018-05-08

申请号：US15065872

申请日：2016-03-10

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Che-Yi Lin ,  En-Chiuan Liou ,  Chia-Hsun Tseng ,  Yi-Ting Chen ,  Chia-Hung Wang ,  Yi-Jing Wang

IPC: G06F17/50 ,  G03F9/00

CPC classification number: G03F9/7003

Abstract: A method of forming an integrated circuit includes the following steps. A substrate including a plurality of exposure fields is provided, and each of the exposure field includes a target portion and a set of alignment marks. Measure the set of alignment marks of each exposure field by a measuring system to obtain alignment data for the respective exposure field. Determine an exposure parameter corresponding to each exposure field and an exposure location on the target portion from the alignment data for the respective exposure field by a calculating system. Feedback the alignment data to a next substrate.

公开(公告)号：US20170220728A1

公开(公告)日：2017-08-03

申请号：US15065872

申请日：2016-03-10

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Che-Yi Lin ,  En-Chiuan Liou ,  Chia-Hsun Tseng ,  Yi-Ting Chen ,  Chia-Hung Wang ,  Yi-Jing Wang

IPC: G06F17/50 ,  G03F1/36

CPC classification number: G03F9/7003

Abstract: A method of forming an integrated circuit includes the following steps. A substrate including a plurality of exposure fields is provided, and each of the exposure field includes a target portion and a set of alignment marks. Measure the set of alignment marks of each exposure field by a measuring system to obtain alignment data for the respective exposure field. Determine an exposure parameter corresponding to each exposure field and an exposure location on the target portion from the alignment data for the respective exposure field by a calculating system. Feedback the alignment data to a next substrate.

公开(公告)号：US09581898B2

公开(公告)日：2017-02-28

申请号：US14685615

申请日：2015-04-14

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： En-Chiuan Liou ,  Chia-Hsun Tseng ,  Tuan-Yen Yu ,  Po-Tsang Chen ,  Yi-Ting Chen

IPC: G03F1/76 ,  G03F1/80 ,  H01L21/033

CPC classification number: G03F1/76 ,  G03F1/54 ,  G03F1/58 ,  G03F1/70 ,  G03F1/72 ,  G03F1/80 ,  H01L21/0337

Abstract: A manufacturing method of a pattern transfer mask includes the following steps. A basic mask is provided. The basic mask includes a plurality of patterns formed by a patterned absorber layer on a substrate according to a first writing layout. A photolithographic process is then performed by the basic mask to obtain individual depth of focus (iDoF) ranges of each of the patterns and a usable depth of focus (UDoF) range of the patterns. At least one constrain pattern dominating the UDoF range is selected from the patterns in the basic mask. The rest of the patterns except the constrain pattern are non-dominating patterns. A second writing layout is then generated for reducing a thickness of the patterned absorber layer in the constrain pattern or in the non-dominating patterns.

Abstract translation: 图案转印掩模的制造方法包括以下步骤。 提供基本的面具。 基本掩模包括根据第一写入布局在基板上由图案化的吸收层形成的多个图案。 然后通过基本掩模执行光刻处理，以获得每种图案的单独焦点深度（iDoF）范围和图案的可用深度（UDoF）范围。 从基本掩码中的图案中选择至少一个主导UDoF范围的约束图案。 除了约束模式之外的其余模式是非主导模式。 然后生成第二写入布局以减小约束图案中的图案化吸收层的厚度或以非主导图案的方式。

公开(公告)号：US20160172308A1

公开(公告)日：2016-06-16

申请号：US15052508

申请日：2016-02-24

Applicant: United Microelectronics Corp.

Inventor： En-Chiuan Liou ,  Teng-Chin Kuo ,  Yi-Ting Chen

IPC: H01L23/544 ,  H01L21/033 ,  H01L23/532

CPC classification number: H01L23/544 ,  G03F7/70633 ,  H01L22/12 ,  H01L22/20 ,  H01L23/53271 ,  H01L2223/54426 ,  H01L2924/0002 ,  H01L2924/00

Abstract: An overlay mark applied to a LELE-type double patterning lithography (DPL) process including a first lithography step, a first etching step, a second lithography step and a second etching step in sequence is described. The overlay mark includes a first x-directional pattern and a first y-directional pattern of a previous layer, second x-directional and y-directional patterns of a current layer defined by the first lithography step, and third x-directional and y-directional patterns of the current layer defined by the second lithography step. The second x-directional patterns and the third x-directional patterns are arranged alternately beside the first x-directional pattern. The second y-directional patterns and the third y-directional patterns are arranged alternately beside the first y-directional pattern.

Abstract translation: 描述了应用于包括第一光刻步骤，第一蚀刻步骤，第二光刻步骤和第二蚀刻步骤的LELE型双重图案化光刻（DPL）工艺的覆盖标记。 覆盖标记包括由第一光刻步骤限定的当前层的先前层，第二x方向和y方向图案的第一x方向图案和第一y方向图案，以及第三x方向和y方向图案， 由第二光刻步骤限定的当前层的方向图案。 第二x方向图案和第三x方向图案交替排列在第一x方向图案旁边。 第二y方向图案和第三y方向图案交替排列在第一y方向图案旁边。

公开(公告)号：US20160093573A1

公开(公告)日：2016-03-31

申请号：US14498217

申请日：2014-09-26

Applicant: United Microelectronics Corp.

Inventor： En-Chiuan Liou ,  Teng-Chin Kuo ,  Yi-Ting Chen

IPC: H01L23/544 ,  H01L21/66 ,  H01L21/311 ,  H01L21/033 ,  H01L23/532 ,  H01L21/027

CPC classification number: H01L23/544 ,  G03F7/70633 ,  H01L22/12 ,  H01L22/20 ,  H01L23/53271 ,  H01L2223/54426 ,  H01L2924/0002 ,  H01L2924/00

Abstract: An overlay mark applied to a LELE-type double patterning lithography (DPL) process including a first lithography step, a first etching step, a second lithography step and a second etching step in sequence is described. The overlay mark includes a first x-directional pattern and a first y-directional pattern of a previous layer, second x-directional and y-directional patterns of a current layer defined by the first lithography step, and third x-directional and y-directional patterns of the current layer defined by the second lithography step. The second x-directional patterns and the third x-directional patterns are arranged alternately beside the first x-directional pattern. The second y-directional patterns and the third y-directional patterns are arranged alternately beside the first y-directional pattern.

Abstract translation: 描述了应用于包括第一光刻步骤，第一蚀刻步骤，第二光刻步骤和第二蚀刻步骤的LELE型双重图案化光刻（DPL）工艺的覆盖标记。 覆盖标记包括由第一光刻步骤限定的当前层的先前层，第二x方向和y方向图案的第一x方向图案和第一y方向图案，以及第三x方向和y方向图案， 由第二光刻步骤限定的当前层的方向图案。 第二x方向图案和第三x方向图案交替排列在第一x方向图案旁边。 第二y方向图案和第三y方向图案交替排列在第一y方向图案旁边。