公开(公告)号：US11417742B1

公开(公告)日：2022-08-16

申请号：US17219829

申请日：2021-03-31

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Chih-Hao Pan ,  Chi-Cheng Huang ,  Kuo-Lung Li ,  Szu-Ping Wang ,  Po-Hsuan Chen ,  Chao-Sheng Cheng

IPC: H01L29/423 ,  H01L29/66 ,  H01L21/28 ,  H01L29/792

Abstract: A memory cell includes a substrate. A first STI and a second STI are embedded within the substrate. The first STI and the second STI extend along a first direction. An active region is disposed on the substrate and between the first STI and the second STI. A control gate is disposed on the substrate and extends along a second direction. The first direction is different from the second direction. A tunneling region is disposed in the active region overlapping the active region. A first trench is embedded within the tunneling region. Two second trenches are respectively embedded within the first STI and the second STI. The control gate fills in the first trench and the second trenches. An electron trapping stack is disposed between the tunneling region and the control gate.

公开(公告)号：US11374109B2

公开(公告)日：2022-06-28

申请号：US16670890

申请日：2019-10-31

Applicant: United Microelectronics Corp.

Inventor： Chih-Hao Pan ,  Chi-Cheng Huang ,  Kuo-Lung Li ,  Szu-Ping Wang ,  Po-Hsuan Chen ,  Chao-Sheng Cheng

IPC: H01L29/66 ,  H01L27/1157

Abstract: A method for fabricating gate structures includes providing a substrate, configured to have a first region and a second region. Dummy gate structures are formed on the substrate at the first and second regions, wherein each of the dummy gate structures has a first gate insulating layer on the substrate and a dummy gate on the first gate insulating layer. An inter-layer dielectric layer is formed over the dummy gate structures. The inter-layer dielectric layer is polished to expose all of the dummy gates. The dummy gates are removed. The first gate insulating layer at the second region is removed. A second gate insulating layer is formed on the substrate at the second region, wherein the first gate insulating layer is thicker than the second insulating layer. Metal gates are formed on the first and the second insulating layer.

公开(公告)号：US20210134979A1

公开(公告)日：2021-05-06

申请号：US16670890

申请日：2019-10-31

Applicant: United Microelectronics Corp.

Inventor： Chih-Hao Pan ,  Chi-Cheng Huang ,  Kuo-Lung Li ,  Szu-Ping Wang ,  Po-Hsuan Chen ,  Chao-Sheng Cheng

IPC: H01L29/66 ,  H01L27/1157

Abstract: A method for fabricating gate structures includes providing a substrate, configured to have a first region and a second region. Dummy gate structures are formed on the substrate at the first and second regions, wherein each of the dummy gate structures has a first gate insulating layer on the substrate and a dummy gate on the first gate insulating layer. An inter-layer dielectric layer is formed over the dummy gate structures. The inter-layer dielectric layer is polished to expose all of the dummy gates. The dummy gates are removed. The first gate insulating layer at the second region is removed. A second gate insulating layer is formed on the substrate at the second region, wherein the first gate insulating layer is thicker than the second insulating layer. Metal gates are formed on the first and the second insulating layer.

公开(公告)号：US10304685B2

公开(公告)日：2019-05-28

申请号：US15675811

申请日：2017-08-14

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Chao-Sheng Cheng

IPC: H01L21/28 ,  H01L21/311 ,  H01L21/8234

Abstract: A manufacturing method of an integrated circuit includes following steps. A dummy gate with a first mask structure formed thereon and a semiconductor gate with a second mask structure formed thereon are formed on a substrate. A top surface of the semiconductor gate is lower than a top surface of the dummy gate. A first removing process is performed to remove the first mask structure and a part of the second mask structure. A dielectric layer is formed covering the dummy gate, the semiconductor gate, and the second mask structure. A second removing process is performed to remove the dielectric layer above the dummy gate. The dummy gate is removed for forming a trench. A metal gate structure is formed in the trench. The semiconductor gate is covered by the second mask structure during the second removing process and the step of removing the dummy gate.

公开(公告)号：US09929164B2

公开(公告)日：2018-03-27

申请号：US15232833

申请日：2016-08-10

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Chao-Sheng Cheng

IPC: H01L29/788 ,  H01L27/11521 ,  H01L29/66 ,  H01L21/306 ,  H01L21/28 ,  H01L23/528

CPC classification number: H01L27/11521 ,  H01L21/28273 ,  H01L21/30604 ,  H01L21/30625 ,  H01L23/528 ,  H01L27/11534 ,  H01L29/42328 ,  H01L29/66545

Abstract: A method for manufacturing an integrated circuit includes following steps. A substrate including a memory region and a core region is provided. At least two semiconductor word lines, two memory cells in between the two semiconductor word lines, and a semiconductor gate in between the two memory cells are formed in the memory region. A transistor device including a dummy gate is formed in the core region, and a height of the dummy gate is larger than a height of the semiconductor word lines. A protecting layer is formed on the semiconductor word lines, the memory cells, the semiconductor gate and the transistor device. A portion of the protecting layer is removed to expose the dummy gate and followed be removing the dummy gate to form a gate trench in the transistor device. Then a metal gate is formed in the gate trench.

公开(公告)号：US11658227B2

公开(公告)日：2023-05-23

申请号：US17569855

申请日：2022-01-06

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Pei-Lun Jheng ,  Chao-Sheng Cheng

IPC: H01L29/49 ,  H01L29/423 ,  H01L21/8234 ,  H01L29/45 ,  H01L27/088

CPC classification number: H01L29/4933 ,  H01L21/82345 ,  H01L21/823443 ,  H01L27/088 ,  H01L29/42372 ,  H01L29/456

Abstract: A method for manufacturing a semiconductor structure is provided. The method comprises the following steps. A first silicon-containing gate electrode is formed on a semiconductor substrate in a first region. A second silicon-containing gate electrode is formed on the semiconductor substrate in a second region. A gate silicide element is formed on an upper surface of the first silicon-containing gate electrode. A source silicide element and a drain silicide element are formed on the semiconductor substrate on opposing sides of the second silicon-containing gate electrode respectively. The gate silicide element, the source silicide element and the drain silicide element are formed simultaneously.

公开(公告)号：US11600709B2

公开(公告)日：2023-03-07

申请号：US17853954

申请日：2022-06-30

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Chih-Hao Pan ,  Chi-Cheng Huang ,  Kuo-Lung Li ,  Szu-Ping Wang ,  Po-Hsuan Chen ,  Chao-Sheng Cheng

IPC: H01L29/792 ,  H01L29/423 ,  H01L29/66 ,  H01L21/28

Abstract: A memory cell includes a substrate. A first STI and a second STI are embedded within the substrate. The first STI and the second STI extend along a first direction. An active region is disposed on the substrate and between the first STI and the second STI. A control gate is disposed on the substrate and extends along a second direction. The first direction is different from the second direction. A tunneling region is disposed in the active region overlapping the active region. A first trench is embedded within the tunneling region. Two second trenches are respectively embedded within the first STI and the second STI. The control gate fills in the first trench and the second trenches. An electron trapping stack is disposed between the tunneling region and the control gate.

公开(公告)号：US20220271137A1

公开(公告)日：2022-08-25

申请号：US17219829

申请日：2021-03-31

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Chih-Hao Pan ,  Chi-Cheng Huang ,  Kuo-Lung Li ,  Szu-Ping Wang ,  Po-Hsuan Chen ,  Chao-Sheng Cheng

IPC: H01L29/423 ,  H01L29/792 ,  H01L21/28 ,  H01L29/66

Abstract: A memory cell includes a substrate. A first STI and a second STI are embedded within the substrate. The first STI and the second STI extend along a first direction. An active region is disposed on the substrate and between the first STI and the second STI. A control gate is disposed on the substrate and extends along a second direction. The first direction is different from the second direction. A tunneling region is disposed in the active region overlapping the active region. A first trench is embedded within the tunneling region. Two second trenches are respectively embedded within the first STI and the second STI. The control gate fills in the first trench and the second trenches. An electron trapping stack is disposed between the tunneling region and the control gate.

公开(公告)号：US11251283B2

公开(公告)日：2022-02-15

申请号：US16832945

申请日：2020-03-27

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Pei-Lun Jheng ,  Chao-Sheng Cheng

IPC: H01L29/45 ,  H01L29/49 ,  H01L29/423 ,  H01L21/8234 ,  H01L27/088

Abstract: A semiconductor structure and a method for manufacturing the same are provided. The semiconductor structure includes a semiconductor substrate, a silicon-containing gate electrode, and at least two gate silicide strips. The silicon-containing gate electrode is on the semiconductor substrate. The at least two gate silicide strips are on an upper surface of the silicon-containing gate electrode.

公开(公告)号：US10056397B2

公开(公告)日：2018-08-21

申请号：US15892387

申请日：2018-02-08

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Chao-Sheng Cheng

IPC: H01L29/788 ,  H01L27/11521 ,  H01L21/306 ,  H01L21/28 ,  H01L27/11534 ,  H01L29/423 ,  H01L29/66 ,  H01L23/528

CPC classification number: H01L27/11521 ,  H01L21/30604 ,  H01L21/30625 ,  H01L23/528 ,  H01L27/11534 ,  H01L29/40114 ,  H01L29/42328 ,  H01L29/66545

Abstract: A method for manufacturing an integrated circuit includes following steps. A substrate including a memory region and a core region is provided. At least two semiconductor word lines, two memory cells in between the two semiconductor word lines, and a semiconductor gate in between the two memory cells are formed in the memory region. A transistor device including a dummy gate is formed in the core region, and a height of the dummy gate is larger than a height of the semiconductor word lines. A protecting layer is formed on the semiconductor word lines, the memory cells, the semiconductor gate and the transistor device. A portion of the protecting layer is removed to expose the dummy gate and followed be removing the dummy gate to form a gate trench in the transistor device. Then a metal gate is formed in the gate trench.