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    ESD GUARD RING STRUCTURE AND FABRICATING METHOD OF THE SAME
    12.
    发明申请
    ESD GUARD RING STRUCTURE AND FABRICATING METHOD OF THE SAME 有权

    公开(公告)号：US20250098333A1

    公开(公告)日：2025-03-20

    申请号：US18380647

    申请日：2023-10-16

    Applicant: UNITED MICROELECTRONICS CORP.

    Inventor： Chia-Chen Sun

    IPC: H01L27/02

    Abstract: An ESD guard ring structure includes numerous first fin structures, numerous second fin structures, numerous first polysilicon conductive lines, numerous second polysilicon conductive lines, numerous third polysilicon conductive lines and numerous single diffusion breaks. Each of the first fin structures includes at least one single diffusion break therein. Each of the single diffusion breaks overlaps one of the third polysilicon conductive lines.

    METHOD OF FORMING A LAYOUT PATTERN AND PHOTOMASK
    13.
    发明公开
    METHOD OF FORMING A LAYOUT PATTERN AND PHOTOMASK 审中-公开

    公开(公告)号：US20240210816A1

    公开(公告)日：2024-06-27

    申请号：US18165937

    申请日：2023-02-08

    Applicant: United Microelectronics Corp.

    Inventor： Chia-Chen Sun ,  En-Chiuan Liou ,  Song-Yi Lin

    IPC: G03F1/70 ,  G03F1/36 ,  G06F30/392

    CPC classification number: G03F1/70 ,  G03F1/36 ,  G06F30/392

    Abstract: A method includes providing a layout pattern to a computer system. The layout pattern includes a first pattern, a second pattern, and a third pattern. A central line defined by connecting a line end of the second pattern and a line end of the third pattern overlaps with a middle portion of the first pattern. An optical proximity correction (OPC) is performed on the layout pattern to form a first auxiliary pattern. The first auxiliary pattern includes a first stripe pattern and a second stripe pattern both extending from the line end of the second pattern. The second stripe pattern is closer to the first pattern than the first stripe pattern, and an extending length of the second stripe pattern is less than an extending length of the first stripe pattern. The layout pattern and the first auxiliary pattern are outputted through the computer system onto a photomask.

    PHOTOMASK STRUCTURE
    14.
    发明公开
    PHOTOMASK STRUCTURE 审中-公开

    公开(公告)号：US20240085780A1

    公开(公告)日：2024-03-14

    申请号：US17965730

    申请日：2022-10-13

    Applicant: United Microelectronics Corp.

    Inventor： Chia-Chen Sun ,  En-Chiuan Liou ,  Song-Yi Lin

    IPC: G03F1/76 ,  G03F1/36

    CPC classification number: G03F1/76 ,  G03F1/36

    Abstract: A photomask structure having a first region and a second region is provided. The layout pattern density of the first region is smaller than the layout pattern density of the second region. The photomask structure includes a first layout pattern, a second layout pattern, and first assist patterns. The first layout pattern is located in the first region and the second region. The second layout pattern is located in the second region. The second layout pattern is located on one side of the first layout pattern. The first assist patterns are located on the first sidewall of the first layout pattern and separated from each other. The first sidewall is adjacent to the second layout pattern. The first assist patterns are adjacent to a boundary between the first region and the second region. The lengths of two adjacent first assist patterns decrease in the direction away from the boundary.

    SEMICONDUCTOR STRUCTURE
    15.
    发明公开
    SEMICONDUCTOR STRUCTURE 审中-公开

    公开(公告)号：US20230411308A1

    公开(公告)日：2023-12-21

    申请号：US17864407

    申请日：2022-07-14

    Applicant: United Microelectronics Corp.

    Inventor： Chia-Chen Sun ,  En-Chiuan Liou

    IPC: H01L23/00 ,  H01L23/522 ,  H01L23/528

    CPC classification number: H01L23/562 ,  H01L23/5226 ,  H01L23/528

    Abstract: Provided is a semiconductor structure including a first and a second conductive layers, and a first group of vias. The second conductive layer is disposed on the first conductive layer. The first group of vias is disposed between and connects the first and the second conductive layer. The first group of vias includes a first, a second, a third and a fourth vias. The first and second vias are arranged in a first column. The third and fourth vias are arranged in a second column. The first via is adjacent to the third via. The second via is adjacent to the fourth via. The extension directions of the first and second vias are orthogonal to each other, the extension directions of the third and the fourth vias are orthogonal to each other, and the extending directions of the first and the third vias are orthogonal to each other.

    DIE SEAL RING STRUCTURE
    16.
    发明公开
    DIE SEAL RING STRUCTURE 审中-公开

    公开(公告)号：US20230260930A1

    公开(公告)日：2023-08-17

    申请号：US17691130

    申请日：2022-03-10

    Applicant: UNITED MICROELECTRONICS CORP.

    Inventor： Chia-Chen Sun ,  En-Chiuan Liou

    IPC: H01L23/00 ,  H01L23/58

    CPC classification number: H01L23/562 ,  H01L23/585

    Abstract: A die seal ring structure includes a metal interconnect structure on a substrate, in which the metal interconnect structure includes an inter-metal dielectric (IMD) layer on the substrate and a first metal interconnection disposed in the IMD layer. Preferably, a first side of the first metal interconnection includes a comb-shape portion in a top view, a second side of the first metal interconnection includes a linear line, a third side of the first metal interconnection includes a linear line, and a fourth side of the first metal interconnection includes a linear line.

    Method for decomposing semiconductor layout pattern
    17.
    发明授权
    Method for decomposing semiconductor layout pattern 有权

    公开(公告)号：US10176289B2

    公开(公告)日：2019-01-08

    申请号：US15462900

    申请日：2017-03-19

    Applicant: UNITED MICROELECTRONICS CORP.

    Inventor： Chia-Chen Sun ,  Yu-Cheng Tung

    IPC: G06F17/50

    Abstract: A method for a semiconductor layout pattern decomposition includes following steps. (a) receiving a semiconductor layout pattern; (b) performing a first separation/decomposition to the semiconductor layout pattern to obtain a grille pattern and a non-grille pattern; (c) recognizing a plurality of intersection regions in the grille pattern and alternately marking the intersection regions with a first region and a second region; (d) performing a second separation/decomposition to the grille pattern to obtain a plurality of first sub-patterns and a plurality of second sub-patterns perpendicular to each other, the first sub-patterns including the first regions, the second sub-patterns including the second regions; and (e) introducing a plurality of first assistance features on the first regions in the first sub-patterns and on the second regions on the second regions in the second sub-patterns, respectively. The step (a) to the step (e) are implemented using a computer.

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