公开(公告)号：US10446689B1

公开(公告)日：2019-10-15

申请号：US16274190

申请日：2019-02-12

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Jen-Po Huang ,  Chien-Ming Lai ,  Yen-Chen Chen ,  Sheng-Yao Huang ,  Hui-Ling Chen ,  Seng Wah Liau ,  Han Chuan Fang

IPC: H01L29/768 ,  H01L29/417 ,  H01L29/66 ,  H01L21/4757 ,  H01L29/786

Abstract: An oxide semiconductor device includes a substrate, a first patterned oxide semiconductor layer, a source electrode, a drain electrode, and a sidewall spacer. The first patterned oxide semiconductor layer is disposed on the substrate. The source electrode and the drain electrode are disposed on the first patterned oxide semiconductor layer. The sidewall spacer is disposed on a sidewall of the first patterned oxide semiconductor layer. The sidewall spacer may be used to improve the performance of blocking impurities from entering the first patterned oxide semiconductor layer via the sidewall, and the electrical performance and the reliability of the oxide semiconductor device may be enhanced accordingly.

公开(公告)号：US10446688B1

公开(公告)日：2019-10-15

申请号：US16190090

申请日：2018-11-13

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Jen-Po Huang ,  Chien-Ming Lai ,  Yen-Chen Chen ,  Sheng-Yao Huang ,  Hui-Ling Chen ,  Seng Wah Liau ,  Han Chuan Fang

IPC: H01L29/786 ,  H01L29/417 ,  H01L21/4757 ,  H01L29/66

Abstract: An oxide semiconductor device includes a substrate, a first patterned oxide semiconductor layer, a source electrode, a drain electrode, and a sidewall spacer. The first patterned oxide semiconductor layer is disposed on the substrate. The source electrode and the drain electrode are disposed on the first patterned oxide semiconductor layer. The sidewall spacer is disposed on a sidewall of the first patterned oxide semiconductor layer. The sidewall spacer may be used to improve the performance of blocking impurities from entering the first patterned oxide semiconductor layer via the sidewall, and the electrical performance and the reliability of the oxide semiconductor device may be enhanced accordingly.

公开(公告)号：US11557558B2

公开(公告)日：2023-01-17

申请号：US16984601

申请日：2020-08-04

Applicant: United Microelectronics Corp.

Inventor： Zhirui Sheng ,  Hui-Ling Chen ,  Chung-Hsing Kuo ,  Chun-Ting Yeh ,  Ming-Tse Lin ,  Chien En Hsu

IPC: H01L21/66 ,  H01L23/00 ,  H01L25/065 ,  H01L25/00

Abstract: A structure of semiconductor device is provided, including a first circuit structure, formed on a first substrate. A first test pad is disposed on the first substrate. A second circuit structure is formed on a second substrate. A second test pad is disposed on the second substrate. A first bonding pad of the first circuit structure is bonded to a second bonding pad of the second circuit structure. One of the first test pad and the second test pad is an inner pad while another one of the first test pad and the second test pad is an outer pad, wherein the outer pad surrounds the inner pad.

公开(公告)号：US11450633B2

公开(公告)日：2022-09-20

申请号：US16781937

申请日：2020-02-04

Applicant: United Microelectronics Corp.

Inventor： Ming-Tse Lin ,  Chung-Hsing Kuo ,  Hui-Ling Chen

IPC: H01L23/00

Abstract: A package structure of a semiconductor device includes a first substrate, a second substrate, and a bonding layer. The bonding layer bonds the first substrate and the second substrate. The bonding layer includes an inner bonding pad pattern and an outer bonding pad pattern formed in a dielectric layer. The outer bonding pad pattern surrounds the inner bonding pad pattern. A first bonding pad density of the outer bonding pad pattern is greater than a second bonding pad density of the inner bonding pad pattern.

公开(公告)号：US11342465B2

公开(公告)日：2022-05-24

申请号：US17140114

申请日：2021-01-03

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Chien-Ming Lai ,  Yen-Chen Chen ,  Jen-Po Huang ,  Sheng-Yao Huang ,  Hui-Ling Chen ,  Qinggang Xing ,  Ding-Lung Chen ,  Li Li Ding ,  Yao-Hung Liu

IPC: H01L29/76 ,  H01L29/786 ,  H01L29/66 ,  H01L29/51 ,  H01L29/423 ,  H01L29/49 ,  H01L29/10

Abstract: An oxide semiconductor field effect transistor (OSFET) includes a first insulating layer, a source, a drain, a U-shaped channel layer and a metal gate. The first insulating layer is disposed on a substrate. The source and the drain are disposed in the first insulating layer. The U-shaped channel layer is sandwiched by the source and the drain. The metal gate is disposed on the U-shaped channel layer, wherein the U-shaped channel layer includes at least an oxide semiconductor layer. The present invention also provides a method for forming said oxide semiconductor field effect transistor.

公开(公告)号：US11164822B1

公开(公告)日：2021-11-02

申请号：US17035385

申请日：2020-09-28

Applicant: United Microelectronics Corp.

Inventor： Chung-Hsing Kuo ,  Chun-Ting Yeh ,  Ming-Tse Lin ,  Hui-Ling Chen ,  Chien-Ming Lai

IPC: H01L23/544 ,  H01L23/488 ,  H01L23/00

Abstract: A structure of semiconductor device is provided. The structure includes a first bonding pattern, formed on a first substrate. A first grating pattern is disposed on the first substrate, having a plurality of first bars extending along a first direction. A second bonding pattern is formed on a second substrate. A second grating pattern, disposed on the second substrate, having a plurality of second bars extending along the first direction. The first bonding pattern is bonded to the second bonding pattern. One of the first grating pattern and the second grating pattern is stacked over and overlapping at the first direction with another one of the first grating pattern and the second grating pattern. A first gap between adjacent two of the first bars is different from a second gap between adjacent two of the second bars.

公开(公告)号：US20210202418A1

公开(公告)日：2021-07-01

申请号：US16781937

申请日：2020-02-04

Applicant: United Microelectronics Corp.

Inventor： MING-TSE LIN ,  Chung-Hsing Kuo ,  Hui-Ling Chen

IPC: H01L23/00

Abstract: A package structure of a semiconductor device includes a first substrate, a second substrate, and a bonding layer. The bonding layer bonds the first substrate and the second substrate. The bonding layer includes an inner bonding pad pattern and an outer bonding pad pattern formed in a dielectric layer. The outer bonding pad pattern surrounds the inner bonding pad pattern. A first bonding pad density of the outer bonding pad pattern is greater than a second bonding pad density of the inner bonding pad pattern.

公开(公告)号：US20200083380A1

公开(公告)日：2020-03-12

申请号：US16154644

申请日：2018-10-08

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Chien-Ming Lai ,  Yen-Chen Chen ,  Jen-Po Huang ,  Sheng-Yao Huang ,  Hui-Ling Chen ,  Qinggang Xing ,  Ding-Lung Chen ,  Li Li Ding ,  Yao-Hung Liu

IPC: H01L29/786 ,  H01L29/66 ,  H01L29/10 ,  H01L29/423 ,  H01L29/49 ,  H01L29/51

Abstract: An oxide semiconductor field effect transistor (OSFET) includes a first insulating layer, a source, a drain, a U-shaped channel layer and a metal gate. The first insulating layer is disposed on a substrate. The source and the drain are disposed in the first insulating layer. The U-shaped channel layer is sandwiched by the source and the drain. The metal gate is disposed on the U-shaped channel layer, wherein the U-shaped channel layer includes at least an oxide semiconductor layer. The present invention also provides a method for forming said oxide semiconductor field effect transistor.

公开(公告)号：US09048246B2

公开(公告)日：2015-06-02

申请号：US13921174

申请日：2013-06-18

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Ming-Te Wei ,  Po-Chao Tsao ,  Ching-Li Yang ,  Chien-Yang Chen ,  Hui-Ling Chen ,  Guan-Kai Huang

IPC: H01L23/00 ,  H01L21/768 ,  H01L21/78 ,  H01L23/58

CPC classification number: H01L23/562 ,  H01L21/76838 ,  H01L21/78 ,  H01L23/585 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A die seal ring is provided. The die seal ring includes a substrate and a first layer extruding from the substrate. The first layer has a first fin ring structure and a layout of the first fin ring structure has a stamp-like shape. In addition, a method for forming a die seal ring is provided. A substrate having an active region is provided. A patterned sacrificial layer is formed on the substrate. A spacer is formed on the sidewall of the patterned sacrificial layer. The patterned sacrificial layer is removed. The substrate is patterned by using the spacer as a mask, thereby simultaneously forming at least a fin structure of a Fin-FET and a first layer of the die seal ring.

Abstract translation: 提供了模具密封环。 模具密封环包括基材和从基材挤出的第一层。 第一层具有第一鳍环结构，并且第一鳍环结构的布局具有戳状形状。 此外，提供了一种用于形成模具密封环的方法。 提供具有有源区的衬底。 在衬底上形成图案化的牺牲层。 在图案化牺牲层的侧壁上形成间隔物。 图案化的牺牲层被去除。 通过使用间隔物作为掩模对衬底进行构图，从而同时形成Fin-FET的鳍结构和模密封环的第一层。

公开(公告)号：US11631771B2

公开(公告)日：2023-04-18

申请号：US17367637

申请日：2021-07-06

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Chien-Ming Lai ,  Yen-Chen Chen ,  Jen-Po Huang ,  Sheng-Yao Huang ,  Hui-Ling Chen ,  Qinggang Xing ,  Ding-Lung Chen ,  Li Li Ding ,  Yao-Hung Liu

IPC: H01L29/76 ,  H01L29/786 ,  H01L29/66 ,  H01L29/51 ,  H01L29/423 ,  H01L29/49 ,  H01L29/10

Abstract: An oxide semiconductor field effect transistor (OSFET) includes a first insulating layer, a source, a drain, a U-shaped channel layer and a metal gate. The first insulating layer is disposed on a substrate. The source and the drain are disposed in the first insulating layer. The U-shaped channel layer is sandwiched by the source and the drain. The metal gate is disposed on the U-shaped channel layer, wherein the U-shaped channel layer includes at least an oxide semiconductor layer. The present invention also provides a method for forming said oxide semiconductor field effect transistor.