公开(公告)号：US08709901B1

公开(公告)日：2014-04-29

申请号：US13864277

申请日：2013-04-17

Applicant: United Microelectronics Corp.

Inventor： Chia-Lung Chang ,  Wu-Sian Sie ,  Jei-Ming Chen ,  Wen-Yi Teng ,  Chih-Chien Liu ,  Jui-Min Lee ,  Chih-Hsun Lin

IPC: H01L21/336

CPC classification number: H01L21/76224 ,  H01L21/31053 ,  H01L21/32105

Abstract: The present invention relates to a method of forming an isolation structure, in which, a trench is formed in a substrate through a hard mask, and deposition, etch back, deposition, planarization, and etch back are performed in the order to form an isolation material layer of the isolation structure after the hard mask is removed. A silicon layer may be formed to cover the trench and original surface of the substrate before the former deposition, or to cover a part of the trench and original surface of the substrate after the former etch back and before the later deposition, to serve as a stop layer for the planarization process. Voids existing within the isolation material layer can be exposed or removed by partially etching the isolation material layer by the former etch back. The later deposition can be performed with a less aspect ratio to avoid forming voids.

Abstract translation: 本发明涉及一种形成隔离结构的方法，其中通过硬掩模在衬底中形成沟槽，并且进行沉积，回蚀刻，沉积，平坦化和回蚀以形成隔离 去除硬掩模后隔离结构的材料层。 可以形成硅层以在前一次沉积之前覆盖衬底的沟槽和原始表面，或者在前面的回蚀刻和稍后的沉积之前覆盖衬底的一部分沟槽和原始表面，以用作 停止层进行平面化处理。 存在于隔离材料层内的空隙可以通过由前面的回蚀部分蚀刻隔离材料层而被暴露或去除。 可以以较小的纵横比进行后续沉积以避免形成空隙。

公开(公告)号：US20140091395A1

公开(公告)日：2014-04-03

申请号：US13633094

申请日：2012-10-01

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Chih-Chien Liu ,  Tzu-Chin Wu ,  Yu-Shu Lin ,  Jei-Ming Chen ,  Wen-Yi Teng

IPC: H01L21/336 ,  H01L27/088 ,  H01L21/28

CPC classification number: H01L29/7843 ,  H01L21/02164 ,  H01L21/324 ,  H01L21/76828 ,  H01L21/76832 ,  H01L21/76834 ,  H01L21/823412 ,  H01L21/823807 ,  H01L21/823864 ,  H01L29/6653

Abstract: A method for fabricating a transistor device including the following processes. First, a semiconductor substrate having a first transistor region is provided. A low temperature deposition process is carried out to form a first tensile stress layer on a transistor within the first transistor region, wherein a temperature of the low temperature deposition process is lower than 300 degree Celsius (° C.). Then, a high temperature annealing process is performed, wherein a temperature of the high temperature annealing process is at least 150° C. higher than a temperature of the low temperature deposition process. Finally, a second tensile stress layer is formed on the first tensile stress layer, wherein the first tensile stress layer has a lower tensile stress than the second tensile stress layer.

Abstract translation: 一种晶体管器件的制造方法，包括以下工序。 首先，提供具有第一晶体管区域的半导体衬底。 进行低温沉积工艺以在第一晶体管区域内的晶体管上形成第一拉伸应力层，其中低温沉积工艺的温度低于300摄氏度（℃）。 然后，进行高温退火处理，其中高温退火工艺的温度比低温沉积工艺的温度高至少150℃。 最后，在第一拉伸应力层上形成第二拉伸应力层，其中第一拉伸应力层具有比第二拉伸应力层低的拉伸应力。

公开(公告)号：US09502305B2

公开(公告)日：2016-11-22

申请号：US14060568

申请日：2013-10-22

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Yi-Wei Chen ,  Teng-Chun Tsai ,  Chien-Chung Huang ,  Jei-Ming Chen ,  Tsai-Fu Hsiao

IPC: H01L21/8238 ,  H01L21/265 ,  H01L29/165 ,  H01L29/66 ,  H01L29/78

CPC classification number: H01L21/823814 ,  H01L21/26506 ,  H01L21/823807 ,  H01L29/165 ,  H01L29/66628 ,  H01L29/7843

Abstract: A CMOS transistor and a method for manufacturing the same are disclosed. A semiconductor substrate having at least a PMOS transistor and an NMOS transistor is provided. The source/drain of the PMOS transistor comprises SiGe epitaxial layer. A carbon implantation process is performed to form a carbon-doped layer in the top portion of the source/drain of the PMOS transistor. A silicide layer is formed on the source/drain. A CESL is formed on the PMOS transistor and the NMOS transistor. The formation of the carbon-doped layer is capable of preventing Ge out-diffusion.

Abstract translation: 公开了一种CMOS晶体管及其制造方法。 提供了至少具有PMOS晶体管和NMOS晶体管的半导体衬底。 PMOS晶体管的源极/漏极包括SiGe外延层。 执行碳注入工艺以在PMOS晶体管的源极/漏极的顶部部分中形成碳掺杂层。 在源极/漏极上形成硅化物层。 在PMOS晶体管和NMOS晶体管上形成CESL。 碳掺杂层的形成能够防止Ge扩散。

公开(公告)号：US09034759B2

公开(公告)日：2015-05-19

申请号：US13740249

申请日：2013-01-13

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Jei-Ming Chen ,  Yuh-Min Lin

IPC: H01L21/768

CPC classification number: H01L21/76819 ,  H01L21/76832 ,  H01L21/76834 ,  H01L21/76837 ,  H01L29/517 ,  H01L29/518 ,  H01L29/66545

Abstract: A method for forming an interlevel dielectric (ILD) layer includes the following steps. A MOS transistor on a substrate is provided. A first undoped oxide layer is deposited to cover the substrate and the MOS transistor. The first undoped oxide layer is planarized. A phosphorus containing oxide layer is deposited on the first undoped oxide layer. A second undoped oxide layer is deposited on the phosphorus containing oxide layer.

Abstract translation: 形成层间电介质（ILD）层的方法包括以下步骤。 提供了衬底上的MOS晶体管。 沉积第一未掺杂的氧化物层以覆盖衬底和MOS晶体管。 第一未掺杂的氧化物层被平坦化。 含磷氧化物层沉积在第一未掺杂氧化物层上。 在含磷氧化物层上沉积第二未掺杂的氧化物层。

公开(公告)号：US08927388B2

公开(公告)日：2015-01-06

申请号：US13677318

申请日：2012-11-15

Applicant: United Microelectronics Corp.

Inventor： Jei-Ming Chen ,  Wen-Yi Teng ,  Chia-Lung Chang ,  Chih-Chien Liu

IPC: H01L21/76 ,  H01L21/762 ,  H01L21/3105 ,  H01L21/768 ,  H01L21/02

CPC classification number: H01L21/76224 ,  H01L21/02164 ,  H01L21/3105 ,  H01L21/76229 ,  H01L21/76819 ,  H01L21/76826 ,  H01L21/76837

Abstract: A method of fabricating a dielectric layer includes the following steps. At first, a dielectric layer is formed on a substrate, and a chemical mechanical polishing (CMP) process is performed on the dielectric layer. Subsequently, a surface treatment process is performed on the dielectric layer after the chemical mechanical polishing process, and the surface treatment process includes introducing an oxygen plasma.

Abstract translation: 制造介电层的方法包括以下步骤。 首先，在基板上形成电介质层，对电介质层进行化学机械研磨（CMP）处理。 随后，在化学机械抛光工艺之后对电介质层进行表面处理工艺，并且表面处理工艺包括引入氧等离子体。

公开(公告)号：US20140199836A1

公开(公告)日：2014-07-17

申请号：US13740249

申请日：2013-01-13

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Jei-Ming Chen ,  Yuh-Min Lin

IPC: H01L21/768

CPC classification number: H01L21/76819 ,  H01L21/76832 ,  H01L21/76834 ,  H01L21/76837 ,  H01L29/517 ,  H01L29/518 ,  H01L29/66545

Abstract: A method for forming an interlevel dielectric (ILD) layer includes the following steps. A MOS transistor on a substrate is provided. A first undoped oxide layer is deposited to cover the substrate and the MOS transistor. The first undoped oxide layer is planarized. A phosphorus containing oxide layer is deposited on the first undoped oxide layer. A second undoped oxide layer is deposited on the phosphorus containing oxide layer.

Abstract translation: 形成层间电介质（ILD）层的方法包括以下步骤。 提供了衬底上的MOS晶体管。 沉积第一未掺杂的氧化物层以覆盖衬底和MOS晶体管。 第一未掺杂的氧化物层被平坦化。 含磷氧化物层沉积在第一未掺杂氧化物层上。 在含磷氧化物层上沉积第二未掺杂的氧化物层。

公开(公告)号：US20140038374A1

公开(公告)日：2014-02-06

申请号：US14060568

申请日：2013-10-22

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Yi-Wei Chen ,  Teng-Chun Tsai ,  Chien-Chung Huang ,  Jei-Ming Chen ,  Tsai-Fu Hsiao

IPC: H01L21/8238

CPC classification number: H01L21/823814 ,  H01L21/26506 ,  H01L21/823807 ,  H01L29/165 ,  H01L29/66628 ,  H01L29/7843

Abstract: A CMOS transistor and a method for manufacturing the same are disclosed. A semiconductor substrate having at least a PMOS transistor and an NMOS transistor is provided. The source/drain of the PMOS transistor comprises SiGe epitaxial layer. A carbon implantation process is performed to form a carbon-doped layer in the top portion of the source/drain of the PMOS transistor. A silicide layer is formed on the source/drain. A CESL is formed on the PMOS transistor and the NMOS transistor. The formation of the carbon-doped layer is capable of preventing Ge out-diffusion.

Abstract translation: 公开了一种CMOS晶体管及其制造方法。 提供了至少具有PMOS晶体管和NMOS晶体管的半导体衬底。 PMOS晶体管的源极/漏极包括SiGe外延层。 执行碳注入工艺以在PMOS晶体管的源极/漏极的顶部部分中形成碳掺杂层。 在源极/漏极上形成硅化物层。 在PMOS晶体管和NMOS晶体管上形成CESL。 碳掺杂层的形成能够防止Ge扩散。