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公开(公告)号：US09362420B2
公开(公告)日：2016-06-07
申请号：US13746296
申请日：2013-01-21
Applicant: UNITED MICROELECTRONICS CORP.
Inventor： Lu-An Chen , Tien-Hao Tang
IPC: H01L23/62 , H01L29/861 , H01L27/02
CPC classification number: H01L29/861 , H01L27/0248 , H01L27/0255 , H01L27/0259 , H01L27/0274
Abstract: The present invention discloses a transistor structure for electrostatic discharge protection. The structure includes a substrate, a doped well, a first doped region, a second doped region and a third doped region. The doped well is disposed in the substrate and has a first conductive type. The first doped region is disposed in the substrate, encompassed by the doped well and has the first conductive type. The second doped region is disposed in the substrate, encompassed by the doped well and has a second conductive type. The third doped region is disposed in the substrate, encompassed by the doped well and has the second conductive type. A gap is disposed between the first doped region and the second doped region.
Abstract translation: 本发明公开了一种用于静电放电保护的晶体管结构。 该结构包括衬底，掺杂阱，第一掺杂区，第二掺杂区和第三掺杂区。 掺杂阱设置在衬底中并且具有第一导电类型。 第一掺杂区域设置在衬底中，由掺杂阱包围并具有第一导电类型。 第二掺杂区域设置在衬底中，被掺杂阱覆盖并具有第二导电类型。 第三掺杂区域设置在衬底中，被掺杂阱包围并具有第二导电类型。 间隙设置在第一掺杂区和第二掺杂区之间。
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公开(公告)号：US20160035823A1
公开(公告)日：2016-02-04
申请号：US14446344
申请日：2014-07-30
Applicant: UNITED MICROELECTRONICS CORP.
Inventor： Lu-An Chen , Tien-Hao Tang
CPC classification number: H01L29/0619 , H01L29/0692 , H01L29/086 , H01L29/0869 , H01L29/0878 , H01L29/1095 , H01L29/7816
Abstract: A semiconductor device includes a substrate, a gate positioned on the substrate, a drain region and a source region formed in the substrate at two respectively sides of the gate, a first well region formed in the substrate, and a plurality of first doped islands formed in the source region. The drain region and the source region include a first conductivity, and the first well region and the first doped islands include a second conductivity. The source region is formed in the first well region, and the first doped islands are spaced apart from the first well region.
Abstract translation: 半导体器件包括衬底，位于衬底上的栅极，在栅极的两个侧面处形成在衬底中的源极区和形成在衬底中的源极区，形成在衬底中的第一阱区，以及形成的多个第一掺杂岛 在源区。 漏区和源极区包括第一导电性，第一阱区和第一掺杂岛包括第二导电性。 源极区形成在第一阱区中，并且第一掺杂岛与第一阱区间隔开。
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公开(公告)号：US20150287838A1
公开(公告)日：2015-10-08
申请号：US14742723
申请日：2015-06-18
Applicant: UNITED MICROELECTRONICS CORP.
Inventor： Chang-Tzu Wang , Ping-Chen Chang , Tien-Hao Tang , Kuan-Cheng Su
IPC: H01L29/861 , H01L29/06
CPC classification number: H01L27/0255 , H01L21/22 , H01L21/265 , H01L21/30604 , H01L21/76 , H01L21/76224 , H01L27/0629 , H01L29/0642 , H01L29/0649 , H01L29/0657 , H01L29/0692 , H01L29/1606 , H01L29/2003 , H01L29/6609 , H01L29/66136 , H01L29/785 , H01L29/861
Abstract: A fin diode structure includes a doped well formed in a substrate, a plurality of fins of first conductivity type and a plurality of fins of second conductivity type protruding from the doped well isolated from ins of first conductivity type by STIs, at least one doped region of first conductivity type in the substrate between the fins of first conductivity type, the STIs and the doped well and connecting with the fins of first conductivity type, and at least one doped region of second conductivity type in the substrate between the fins of second conductivity type, the STIs and the doped well and connecting with the fins of second conductivity type. The doping concentration of the fins of first conductivity type is greater than that of the doped region of first conductivity type whose doping concentration is greater than that of the doped well of first conductivity type.
Abstract translation: 翅片二极管结构包括在衬底中形成的掺杂阱，第一导电类型的多个鳍和第二导电类型的多个翅片，其通过STI从与第一导电类型的绝缘体隔离的掺杂阱突出，至少一个掺杂区域 第一导电类型的翅片之间的衬底中的第一导电类型，STI和掺杂阱并且与第一导电类型的鳍连接并且在第二导电类型的鳍之间的衬底中的至少一个第二导电类型的掺杂区域 类型，STI和掺杂阱，并与第二导电类型的鳍连接。 第一导电类型的散热片的掺杂浓度大于其掺杂浓度大于第一导电类型的掺杂阱的第一导电类型的掺杂区域的掺杂浓度。
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公开(公告)号：US09041110B2
公开(公告)日：2015-05-26
申请号：US13848069
申请日：2013-03-21
Applicant: UNITED MICROELECTRONICS CORP.
Inventor： Lu-An Chen , Tien-Hao Tang
CPC classification number: H01L27/0266 , H01L23/60 , H01L29/0653 , H01L29/0847 , H01L29/66659 , H01L29/78 , H01L29/7835 , H01L2924/0002 , H01L2924/00
Abstract: A semiconductor device includes a substrate, a gate positioned on the substrate, a drain region and a source region formed at respective two sides of the gate in the substrate, at least a first doped region formed in the drain region, and at least a first well having the first doped region formed therein. The source region and the drain region include a first conductivity type, the first doped region and the first well include a second conductivity type, and the first conductivity type and the second conductivity type are complementary to each other.
Abstract translation: 半导体器件包括衬底，位于衬底上的栅极，形成在衬底中的栅极的相应两侧处的漏极区域和源极区域，形成在漏极区域中的至少第一掺杂区域，以及至少第一 其中形成有第一掺杂区。 源区和漏区包括第一导电类型，第一掺杂区和第一阱包括第二导电类型，并且第一导电类型和第二导电类型彼此互补。
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公开(公告)号：US20150123184A1
公开(公告)日：2015-05-07
申请号：US14071670
申请日：2013-11-05
Applicant: UNITED MICROELECTRONICS CORP.
Inventor： Chang-Tzu Wang , Yu-Chun Chen , Tien-Hao Tang , Kuan-Cheng Su
IPC: H01L27/092 , H01L27/06 , H01L23/60 , H01L29/78
CPC classification number: H01L27/0925 , H01L21/823892 , H01L27/0274 , H01L27/0629 , H01L27/092 , H01L27/0924 , H01L29/785
Abstract: A CMOS device includes a substrate, a pMOS transistor and an nMOS transistor formed on the substrate, and a gated diode. The gated diode includes a floating gate formed on the substrate in between the pMOS transistor and the nMOS transistor and a pair of a p-doped region and an n-doped region formed in the substrate and between the pMOS transistor and the nMOS transistor. The n-doped region is formed between the floating gate and the nMOS transistor, and the p-doped region is formed between the floating gate and the pMOS transistor.
Abstract translation: CMOS器件包括衬底，pMOS晶体管和形成在衬底上的nMOS晶体管，以及门控二极管。 门控二极管包括形成在pMOS晶体管和nMOS晶体管之间的衬底上的浮置栅极和形成在衬底中以及在pMOS晶体管和nMOS晶体管之间的一对p掺杂区域和n掺杂区域。 在浮置栅极和nMOS晶体管之间形成n掺杂区域，并且在浮置栅极和pMOS晶体管之间形成p掺杂区域。
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Patent Agency Ranking
公开(公告)号：US20150054132A1
公开(公告)日：2015-02-26
申请号：US13974939
申请日：2013-08-23
Applicant: United Microelectronics Corp.
Inventor： Chang-Tzu Wang , Pei-Shan Tseng , Tien-Hao Tang
CPC classification number: H01L29/735 , H01L27/0259 , H01L29/0821 , H01L29/6625 , H01L29/861
Abstract: Provided is a lateral BJT including a substrate, a well region, an area, at least one lightly doped region, a first doped region, and a second doped region. The substrate is of a first conductivity type. The well region is of a second conductivity type and is in the substrate. The area is in the well region. The at least one lightly doped region is in the well region below the area. The first doped region and the second doped region are of the first conductivity type and are in the well region on both sides of the area. The first doped region is connected to a cathode. The second doped region is connected to an anode, wherein the doping concentration of the at least one lightly doped region is lower than that of each of the first doped region, the second doped region, and the well region.
Abstract translation: 提供了包括衬底，阱区，区域，至少一个轻掺杂区域，第一掺杂区域和第二掺杂区域的横向BJT。 衬底是第一导电类型。 阱区是第二导电类型并且在衬底中。 该地区在该地区。 该至少一个轻掺杂区域位于该区域下方的阱区域中。 第一掺杂区域和第二掺杂区域是第一导电类型并且在该区域两侧的阱区域中。 第一掺杂区域连接到阴极。 第二掺杂区域连接到阳极，其中至少一个轻掺杂区域的掺杂浓度低于第一掺杂区域，第二掺杂区域和阱区域中的每一个的掺杂浓度。
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公开(公告)号：US20140203367A1
公开(公告)日：2014-07-24
申请号：US13746296
申请日：2013-01-21
Applicant: UNITED MICROELECTRONICS CORP.
Inventor： Lu-An Chen , Tien-Hao Tang
IPC: H01L27/02
CPC classification number: H01L29/861 , H01L27/0248 , H01L27/0255 , H01L27/0259 , H01L27/0274
Abstract: The present invention discloses a transistor structure for electrostatic discharge protection. The structure includes a substrate, a doped well, a first doped region, a second doped region and a third doped region. The doped well is disposed in the substrate and has a first conductive type. The first doped region is disposed in the substrate, encompassed by the doped well and has the first conductive type. The second doped region is disposed in the substrate, encompassed by the doped well and has a second conductive type. The third doped region is disposed in the substrate, encompassed by the doped well and has the second conductive type. A gap is disposed between the first doped region and the second doped region.
Abstract translation: 本发明公开了一种用于静电放电保护的晶体管结构。 该结构包括衬底，掺杂阱，第一掺杂区，第二掺杂区和第三掺杂区。 掺杂阱设置在衬底中并且具有第一导电类型。 第一掺杂区域设置在衬底中，由掺杂阱包围并具有第一导电类型。 第二掺杂区域设置在衬底中，被掺杂阱覆盖并具有第二导电类型。 第三掺杂区域设置在衬底中，被掺杂阱包围并具有第二导电类型。 间隙设置在第一掺杂区和第二掺杂区之间。
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公开(公告)号：US12211833B2
公开(公告)日：2025-01-28
申请号：US17742392
申请日：2022-05-11
Applicant: UNITED MICROELECTRONICS CORP.
Inventor： Hou-Jen Chiu , Mei-Ling Chao , Tien-Hao Tang , Kuan-Cheng Su
IPC: H01L27/02
Abstract: An electrostatic discharge protection structure includes a semiconductor substrate, a gate structure disposed on the semiconductor substrate, a first well region of a first conductivity type disposed in the semiconductor substrate, a first doped region of the first conductivity type, a second doped region of a second conductivity type, a third doped region of the first conductivity type, and a fourth doped region of the second conductivity type. The first and second doped regions are disposed in the first well region and connected with each other. The second doped region is an emitter of a first bipolar junction transistor. The third and fourth doped regions are disposed in the semiconductor substrate and connected with each other. The third and second doped regions are located at two opposite sides of the gate structure in a first horizontal direction. The third doped region is an emitter of a second bipolar junction transistor.
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公开(公告)号：US20240194668A1
公开(公告)日：2024-06-13
申请号：US18105256
申请日：2023-02-03
Applicant: UNITED MICROELECTRONICS CORP.
Inventor： Yu-Hsuan Lin , Hou-Jen Chiu , Mei-Ling Chao , Tien-Hao Tang , Kuan-Cheng Su
IPC: H01L27/02 , H01L27/082 , H01L29/08
CPC classification number: H01L27/0259 , H01L27/082 , H01L29/0808 , H01L29/0821 , H01L29/735
Abstract: An electrostatic discharge protection structure includes a semiconductor substrate and a first n-type well region, a p-type well region, a first p-type doped region, a second p-type doped region, and an isolation structure disposed in the semiconductor substrate. The p-type well region is located adjacent to the first n-type well region. The first p-type doped region and the second p-type doped region are located above the first n-type well region and the p-type well region, respectively. A first portion of the isolation structure is located between the first p-type doped region and the second p-type doped region in a horizontal direction. An edge of the first n-type well region is located under the first portion. A distance between the first p-type doped region and the edge of the first n-type well region in the horizontal direction is less than a length of the first portion in the horizontal direction.
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公开(公告)号：US11004840B2
公开(公告)日：2021-05-11
申请号：US16200662
申请日：2018-11-27
Applicant: UNITED MICROELECTRONICS CORP.
Inventor： Shih-Che Yen , Tien-Hao Tang , Chun Chiang , Kuan-Cheng Su
Abstract: A silicon controlled rectifier includes a substrate, an N-type well, a P-type well, a gate structure, a first N-type doped region, a second N-type doped region, a first P-type doped region, a second P-type doped region, a first STI, and a second STI. The N-type well and the P-type well are disposed in the substrate. The gate structure is disposed on the P-type well. The first N-type doped region is disposed in the N-type well at one side of the gate structure. The second N-type doped region is disposed in the P-type well at another side of the gate structure. The first P-type doped region is disposed in the N-type well. The second P-type doped region is disposed in the P-type well. The first STI is between the first N-type and first P-type doped regions. The second STI is between the second N-type and second P-type doped regions.
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