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    SEMICONDUCTOR MEMORY DEVICE
    12.
    发明申请
    SEMICONDUCTOR MEMORY DEVICE 审中-公开

    公开(公告)号：US20180286474A1

    公开(公告)日：2018-10-04

    申请号：US15589985

    申请日：2017-05-08

    Applicant: UNITED MICROELECTRONICS CORP.

    Inventor： Chien-Hung Chen ,  Meng-Ping Chuang ,  Tong-Yu Chen ,  Yu-Tse Kuo

    IPC: G11C11/406 ,  G11C11/407

    CPC classification number: G11C5/025 ,  G11C11/412 ,  H01L27/11 ,  H01L27/1104

    Abstract: A semiconductor memory device including a memory cell having a plurality of memory cells, a first P-type well region, a second P-type well region, and an N-type well region disposed between the first P-Type well region and the second P-type well region. The semiconductor memory element defines a plurality of first regions and a plurality of second regions, each of the first regions and each of the second regions including one of the memory cells, each of the second regions further includes at least two first voltage providing contacts, and at least one second voltage providing contact, wherein the first voltage providing contacts and the second voltage providing contact are not located within each first region.

    Semiconductor structure and method of forming a harmonic-effect-suppression structure
    13.
    发明授权
    Semiconductor structure and method of forming a harmonic-effect-suppression structure 有权
    形成谐波抑制结构的半导体结构和方法

    公开(公告)号：US09048285B2

    公开(公告)日：2015-06-02

    申请号：US13932009

    申请日：2013-07-01

    Applicant: UNITED MICROELECTRONICS CORP.

    Inventor： Tong-Yu Chen ,  Kuo-Yuh Yang

    IPC: H01L21/762 ,  H01L29/06 ,  H01L21/768

    CPC classification number: H01L21/76224 ,  H01L21/02532 ,  H01L21/02595 ,  H01L21/02664 ,  H01L21/26506 ,  H01L21/30604 ,  H01L21/30625 ,  H01L21/3081 ,  H01L21/76232 ,  H01L21/7624 ,  H01L21/76283 ,  H01L21/76898 ,  H01L29/0649

    Abstract: A semiconductor structure includes a SOI/BOX semiconductor substrate, a device, a deep trench, a silicon layer, and a dielectric layer. The deep trench is adjacent to the device and extends through a shallow trench isolation layer within the SOI layer and the BOX layer and into the base semiconductor substrate. The silicon layer is disposed within a lower portion of the deep trench. The silicon layer has a top surface height substantially the same as or lower than a top surface height of the base semiconductor substrate. The dielectric layer is disposed within the deep trench and on the silicon layer. The deep trench can be formed before or after formation of an interlayer dielectric.

    Abstract translation: 半导体结构包括SOI / BOX半导体衬底，器件，深沟槽，硅层和电介质层。 深沟槽与器件相邻，并延伸穿过SOI层和BOX层内的浅沟槽隔离层并进入基底半导体衬底。 硅层设置在深沟槽的下部内。 硅层具有与基底半导体衬底的顶表面高度基本相同或更低的顶表面高度。 电介质层设置在深沟槽内和硅层上。 深沟槽可以在形成层间电介质之前或之后形成。

    FIELD EFFECT TRANSISTOR WITH FIN STRUCTURE
    14.
    发明申请
    FIELD EFFECT TRANSISTOR WITH FIN STRUCTURE 审中-公开
    具有结构的场效应晶体管

    公开(公告)号：US20140374841A1

    公开(公告)日：2014-12-25

    申请号：US14483165

    申请日：2014-09-11

    Applicant: UNITED MICROELECTRONICS CORP.

    Inventor： Chih-Jung Wang ,  Tong-Yu Chen

    IPC: H01L29/78 ,  H01L29/06

    CPC classification number: H01L29/7851 ,  H01L29/0649 ,  H01L29/66545 ,  H01L29/66818

    Abstract: A FET with a fin structure includes a substrate, an isolation structure and a gate structure. The substrate includes at least one fin structure. The fin structure includes two source/drain regions and a gate channel region between the two source/drain regions. The isolation structure is disposed on the substrate and surrounds the fin structure to expose an upper portion of the fin structure. A width of the gate channel region of the exposed upper portion of the fin structure is less than each of widths of the source region and the drain region. A gate structure covering two sidewalls of the gate channel region of the exposed upper portion of the fin structure is formed. Two sidewalls of the gate structure contact two facing sidewalls of the two source/drain regions, respectively.

    Abstract translation: 具有翅片结构的FET包括衬底，隔离结构和栅极结构。 衬底包括至少一个翅片结构。 鳍结构包括两个源极/漏极区域和两个源极/漏极区域之间的栅极沟道区域。 隔离结构设置在基板上并且围绕翅片结构以暴露翅片结构的上部。 翅片结构的暴露的上部的栅极沟道区域的宽度小于源极区域和漏极区域的宽度。 形成覆盖翅片结构的暴露的上部的栅极沟道区的两个侧壁的栅极结构。 栅极结构的两个侧壁分别与两个源极/漏极区的两个相对的侧壁接触。

    Semiconductor memory device
    15.
    发明授权
    Semiconductor memory device 有权

    公开(公告)号：US10134449B2

    公开(公告)日：2018-11-20

    申请号：US15589985

    申请日：2017-05-08

    Applicant: UNITED MICROELECTRONICS CORP.

    Inventor： Chien-Hung Chen ,  Meng-Ping Chuang ,  Tong-Yu Chen ,  Yu-Tse Kuo

    IPC: G11C5/02 ,  G11C11/412 ,  H01L27/11

    Abstract: A semiconductor memory device including a memory cell having a plurality of memory cells, a first P-type well region, a second P-type well region, and an N-type well region disposed between the first P-Type well region and the second P-type well region. The semiconductor memory element defines a plurality of first regions and a plurality of second regions, each of the first regions and each of the second regions including one of the memory cells, each of the second regions further includes at least two first voltage providing contacts, and at least one second voltage providing contact, wherein the first voltage providing contacts and the second voltage providing contact are not located within each first region.

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