公开(公告)号：US09023726B1

公开(公告)日：2015-05-05

申请号：US14082200

申请日：2013-11-18

Applicant: United Microelectronics Corp.

Inventor： Wei Cheng ,  Ming Sheng Xu ,  Duan Quan Liao ,  Yikun Chen ,  Ching Hwa Tey

IPC: H01L21/3205 ,  H01L21/28 ,  H01L21/8234

CPC classification number: H01L21/28132 ,  H01L21/28273 ,  H01L21/823468 ,  H01L27/11524

Abstract: A method of fabricating a semiconductor device includes the following steps. At least a first gate stack layer and at least a second gate stack layer protruding from a conductive layer on a substrate are provided. Subsequently, two spacers and a protective layer are formed on the conductive layer, and the two spacers and the protective layer jointly surround the protruded first gate stack layer and the protruded second gate stack layer. The two spacers and the protective layer are used as a mask to remove a part of the conductive layer. Afterwards, the two spacers and the protective layer are removed.

Abstract translation: 制造半导体器件的方法包括以下步骤。 提供至少一个第一栅堆叠层和至少一个从衬底上的导电层突出的第二栅堆叠层。 随后，在导电层上形成两个间隔物和保护层，两个间隔物和保护层共同围绕突出的第一栅叠层和突出的第二栅堆叠层。 将两个间隔物和保护层用作掩模以去除导电层的一部分。 之后，取下两个间隔物和保护层。

公开(公告)号：US09941161B2

公开(公告)日：2018-04-10

申请号：US14838374

申请日：2015-08-28

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Duan Quan Liao ,  Yikun Chen ,  Ching Hwa Tey

IPC: H01L21/768 ,  H01L21/306 ,  H01L29/78 ,  H01L29/66 ,  H01L21/3105 ,  H01L21/283

CPC classification number: H01L21/76897 ,  H01L21/283 ,  H01L21/30625 ,  H01L21/31051 ,  H01L21/76829 ,  H01L29/6653 ,  H01L29/66545 ,  H01L29/78 ,  H01L29/785

Abstract: A method for fabricating semiconductor device is disclosed. The method includes the steps of: providing a substrate having a gate structure thereon, a first hard mask atop the gate structure, and an interlayer dielectric (ILD) layer around the gate structure and the first hard mask; removing part of the first hard mask; forming a second hard mask layer on the first hard mask and the ILD layer; and planarizing part of the second hard mask layer to form a second hard mask on the first hard mask.

公开(公告)号：US09276057B2

公开(公告)日：2016-03-01

申请号：US14165535

申请日：2014-01-27

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Duan Quan Liao ,  Yikun Chen ,  Ching Hwa Tey ,  Xiao Zhong Zhu

IPC: H01L29/94 ,  H01L49/02 ,  H01L21/768 ,  H01L23/522 ,  H01L23/532 ,  H01L27/108

CPC classification number: H01L28/75 ,  H01L21/76807 ,  H01L23/5223 ,  H01L23/53238 ,  H01L23/5329 ,  H01L23/53295 ,  H01L27/10808 ,  H01L27/10852 ,  H01L28/91 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A capacitor structure includes a substrate with a plurality of dielectric layers sequentially formed thereon, a trench formed in the dielectric layers, wherein the trench is composed of at least two interconnected dual damascene recesses, each dual damascene recess formed in one dielectric layer; and a capacitor multilayer disposed on the sidewall of the trench.

Abstract translation: 电容器结构包括其上顺序地形成有多个电介质层的衬底，形成在电介质层中的沟槽，其中沟槽由至少两个互连的双镶嵌凹部组成，每个双镶嵌凹部形成在一个介电层中; 以及设置在沟槽的侧壁上的电容器多层。

公开(公告)号：US20150214293A1

公开(公告)日：2015-07-30

申请号：US14165535

申请日：2014-01-27

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Duan Quan Liao ,  Yikun Chen ,  CHING HWA TEY ,  Xiao Zhong Zhu

IPC: H01L49/02 ,  H01L27/108

CPC classification number: H01L28/75 ,  H01L21/76807 ,  H01L23/5223 ,  H01L23/53238 ,  H01L23/5329 ,  H01L23/53295 ,  H01L27/10808 ,  H01L27/10852 ,  H01L28/91 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A capacitor structure includes a substrate with a plurality of dielectric layers sequentially formed thereon, a trench formed in the dielectric layers, wherein the trench is composed of at least two interconnected dual damascene recesses, each dual damascene recess formed in one dielectric layer; and a capacitor multilayer disposed on the sidewall of the trench.

Abstract translation: 电容器结构包括其上顺序地形成有多个电介质层的衬底，形成在电介质层中的沟槽，其中沟槽由至少两个互连的双镶嵌凹部组成，每个双镶嵌凹部形成在一个介电层中; 以及设置在沟槽的侧壁上的电容器多层。

公开(公告)号：US20140252482A1

公开(公告)日：2014-09-11

申请号：US14288369

申请日：2014-05-27

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Rai-Min Huang ,  Sheng-Huei Dai ,  Chen-Hua Tsai ,  Duan Quan Liao ,  Yikun Chen ,  Xiao Zhong Zhu

IPC: H01L29/06 ,  H01L29/78

CPC classification number: H01L29/0653 ,  H01L27/10826 ,  H01L27/10879 ,  H01L29/66795 ,  H01L29/785 ,  H01L29/7854

Abstract: A FINFET transistor structure includes a substrate including a fin structure. Two combined recesses embedded within the substrate, wherein each of the combined recesses includes a first recess extending in a vertical direction and a second recess extending in a lateral direction, the second recess has a protruding side extending to and under the fin structure. Two filling layers respectively fill in the combined recesses. A gate structure crosses the fin structure.

Abstract translation: FINFET晶体管结构包括包括鳍结构的衬底。 嵌入在基板内的两个组合的凹槽，其中每个组合的凹槽包括沿垂直方向延伸的第一凹部和沿横向方向延伸的第二凹槽，第二凹部具有延伸到翅片结构下方和下方的突出侧。 两个填充层分别填充组合的凹部。 栅极结构穿过鳍结构。