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    Method of fabricating semiconductor device
    1.
    发明授权
    Method of fabricating semiconductor device 有权
    制造半导体器件的方法

    公开(公告)号：US09583594B2

    公开(公告)日：2017-02-28

    申请号：US14829649

    申请日：2015-08-19

    Applicant: UNITED MICROELECTRONICS CORP.

    Inventor： Duan Quan Liao ,  Yikun Chen ,  Ching Hwa Tey

    IPC: H01L23/535 ,  H01L29/66 ,  H01L21/768 ,  H01L29/06

    CPC classification number: H01L21/0337 ,  H01L21/3086 ,  H01L21/31144 ,  H01L21/76816 ,  H01L29/0657 ,  H01L29/66553

    Abstract: A semiconductor device and a method of fabricating the same, the semiconductor device includes a hard mask layer and a plurality of spacers. The hard mask layer is disposed on a target layer and has a first material and a second material. The spacers are disposed on the hard mask layer, wherein a first portion of the spacers is disposed on the first material, and a second portion of the spacers is disposed on the second material.

    Abstract translation: 半导体器件及其制造方法，半导体器件包括硬掩模层和多个间隔物。 硬掩模层设置在目标层上并具有第一材料和第二材料。 间隔物设置在硬掩模层上，其中间隔物的第一部分设置在第一材料上，间隔物的第二部分设置在第二材料上。

    SEMICONDUCTOR PROCESS
    2.
    发明申请
    SEMICONDUCTOR PROCESS 有权
    半导体工艺

    公开(公告)号：US20150348789A1

    公开(公告)日：2015-12-03

    申请号：US14288399

    申请日：2014-05-28

    Applicant: UNITED MICROELECTRONICS CORP.

    Inventor： Duan Quan Liao ,  Wei Cheng ,  Yikun Chen ,  CHING HWA TEY ,  Xiao Zhong Zhu

    IPC: H01L21/28

    CPC classification number: H01L21/28273 ,  H01L27/11521 ,  H01L27/11534

    Abstract: A semiconductor process includes the following steps. A first gate is formed on a substrate, wherein the first gate includes a stacked gate on the substrate and a cap on the stacked gate. A spacer material is formed to conformally cover the first gate and the substrate. The spacer material is etched to form a spacer on a side of the first gate and a block on the other side of the first gate corresponding to the side. A material covers the substrate, the block, the first gate and the spacer, wherein the top surface of the material is a flat surface. The block, the spacer and the material are pulled down with the same pulling selectivity so that an assisting gate is formed from the block and a selective gate is formed from the spacer.

    Abstract translation: 半导体工艺包括以下步骤。 第一栅极形成在衬底上，其中第一栅极包括衬底上的堆叠栅极和堆叠栅极上的帽。 形成间隔物材料以保形地覆盖第一栅极和衬底。 蚀刻间隔材料以在第一栅极的一侧上形成间隔物，并且在第一栅极的另一侧上对应于侧面的块。 材料覆盖基板，块，第一栅极和间隔件，其中材料的顶表面是平坦的表面。 块，间隔物和材料以相同的拉拔选择性被拉下，使得从块形成辅助栅极，并且由间隔物形成选择栅极。

    FINFET TRANSISTOR STRUCTURE AND METHOD FOR MAKING THE SAME
    3.
    发明申请
    FINFET TRANSISTOR STRUCTURE AND METHOD FOR MAKING THE SAME 审中-公开
    FINFET晶体管结构及其制造方法

    公开(公告)号：US20140225197A1

    公开(公告)日：2014-08-14

    申请号：US14261441

    申请日：2014-04-25

    Applicant: UNITED MICROELECTRONICS CORP.

    Inventor： Rai-Min Huang ,  Sheng-Huei Dai ,  Chen-Hua Tsai ,  Duan Quan Liao ,  Yikun Chen ,  Xiao Zhong Zhu

    IPC: H01L29/78 ,  H01L29/66

    CPC classification number: H01L29/0653 ,  H01L27/10826 ,  H01L27/10879 ,  H01L29/66795 ,  H01L29/785 ,  H01L29/7854

    Abstract: A FINFET transistor structure includes a substrate, a fin structure, an insulating layer and a gate structure. The fin structure is disposed on the substrate and directly connected to the substrate. Besides, the fin structure includes a fin conductive layer and a bottle neck. The insulating layer covers the substrate and has a protruding side which is formed by partially surrounding the bottle neck of the fin structure, and a bottom side in direct contact with the substrate so that the protruding side extend to and under the fin structure. The gate structure partially surrounds the fin structure.

    Abstract translation: FINFET晶体管结构包括衬底，鳍结构，绝缘层和栅极结构。 翅片结构设置在基板上并直接连接到基板。 此外，翅片结构包括翅片导电层和瓶颈。 绝缘层覆盖基板，并且具有通过部分地围绕翅片结构的瓶颈而形成的突出侧，以及与基板直接接触的底侧，使得突出侧延伸到翅片结构的下方。 门结构部分地围绕翅片结构。

    METHOD FOR FABRICATING SEMICONDUCTOR DEVICE
    4.
    发明申请
    METHOD FOR FABRICATING SEMICONDUCTOR DEVICE 有权
    制造半导体器件的方法

    公开(公告)号：US20170040179A1

    公开(公告)日：2017-02-09

    申请号：US14838374

    申请日：2015-08-28

    Applicant: United Microelectronics Corp.

    Inventor： Duan Quan Liao ,  Yikun Chen ,  CHING HWA TEY

    IPC: H01L21/3105 ,  H01L21/32 ,  H01L21/768 ,  H01L21/283

    CPC classification number: H01L21/76897 ,  H01L21/283 ,  H01L21/30625 ,  H01L21/31051 ,  H01L21/76829 ,  H01L29/6653 ,  H01L29/66545 ,  H01L29/78 ,  H01L29/785

    Abstract: A method for fabricating semiconductor device is disclosed. The method includes the steps of: providing a substrate having a gate structure thereon, a first hard mask atop the gate structure, and an interlayer dielectric (ILD) layer around the gate structure and the first hard mask; removing part of the first hard mask; forming a second hard mask layer on the first hard mask and the ILD layer; and planarizing part of the second hard mask layer to form a second hard mask on the first hard mask.

    Abstract translation: 公开了半导体器件的制造方法。 该方法包括以下步骤：提供其上具有栅极结构的衬底，栅极结构顶部的第一硬掩模和围绕栅极结构和第一硬掩模的层间电介质（ILD）层; 去除第一硬掩模的一部分; 在所述第一硬掩模和所述ILD层上形成第二硬掩模层; 以及平坦化所述第二硬掩模层的部分以在所述第一硬掩模上形成第二硬掩模。

    METHOD OF FABRICATING SEMICONDUCTOR DEVICE
    5.
    发明申请
    METHOD OF FABRICATING SEMICONDUCTOR DEVICE 有权
    制造半导体器件的方法

    公开(公告)号：US20170025519A1

    公开(公告)日：2017-01-26

    申请号：US14829649

    申请日：2015-08-19

    Applicant: UNITED MICROELECTRONICS CORP.

    Inventor： Duan Quan Liao ,  Yikun Chen ,  CHING HWA TEY

    IPC: H01L29/66 ,  H01L23/535 ,  H01L29/06 ,  H01L21/768

    CPC classification number: H01L21/0337 ,  H01L21/3086 ,  H01L21/31144 ,  H01L21/76816 ,  H01L29/0657 ,  H01L29/66553

    Abstract: A semiconductor device and a method of fabricating the same, the semiconductor device includes a hard mask layer and a plurality of spacers. The hard mask layer is disposed on a target layer and has a first material and a second material. The spacers are disposed on the hard mask layer, wherein a first portion of the spacers is disposed on the first material, and a second portion of the spacers is disposed on the second material.

    Abstract translation: 半导体器件及其制造方法，半导体器件包括硬掩模层和多个间隔物。 硬掩模层设置在目标层上并具有第一材料和第二材料。 间隔物设置在硬掩模层上，其中间隔物的第一部分设置在第一材料上，间隔物的第二部分设置在第二材料上。

    Semiconductor process
    9.
    发明授权
    Semiconductor process 有权
    半导体工艺

    公开(公告)号：US09401280B2

    公开(公告)日：2016-07-26

    申请号：US14288399

    申请日：2014-05-28

    Applicant: UNITED MICROELECTRONICS CORP.

    Inventor： Duan Quan Liao ,  Wei Cheng ,  Yikun Chen ,  Ching Hwa Tey ,  Xiao Zhong Zhu

    IPC: H01L21/28 ,  H01L27/115

    CPC classification number: H01L21/28273 ,  H01L27/11521 ,  H01L27/11534

    Abstract: A semiconductor process includes the following steps. A first gate is formed on a substrate, wherein the first gate includes a stacked gate on the substrate and a cap on the stacked gate. A spacer material is formed to conformally cover the first gate and the substrate. The spacer material is etched to form a spacer on a side of the first gate and a block on the other side of the first gate corresponding to the side. A material covers the substrate, the block, the first gate and the spacer, wherein the top surface of the material is a flat surface. The block, the spacer and the material are pulled down with the same pulling selectivity so that an assisting gate is formed from the block and a selective gate is formed from the spacer.

    Abstract translation: 半导体工艺包括以下步骤。 第一栅极形成在衬底上，其中第一栅极包括衬底上的堆叠栅极和堆叠栅极上的帽。 形成间隔物材料以保形地覆盖第一栅极和衬底。 蚀刻间隔材料以在第一栅极的一侧上形成间隔物，并且在第一栅极的另一侧上对应于侧面的块。 材料覆盖基板，块，第一栅极和间隔件，其中材料的顶表面是平坦的表面。 块，间隔物和材料以相同的拉拔选择性被拉下，使得从块形成辅助栅极，并且由间隔物形成选择栅极。

    METHOD OF FABRICATING SEMICONDUCTOR DEVICE
    10.
    发明申请
    METHOD OF FABRICATING SEMICONDUCTOR DEVICE 有权
    制造半导体器件的方法

    公开(公告)号：US20150140800A1

    公开(公告)日：2015-05-21

    申请号：US14082200

    申请日：2013-11-18

    Applicant: UNITED MICROELECTRONICS CORP.

    Inventor： Wei Cheng ,  Ming Sheng Xu ,  Duan Quan Liao ,  Yikun Chen ,  CHING HWA TEY

    IPC: H01L21/28 ,  H01L21/8234

    CPC classification number: H01L21/28132 ,  H01L21/28273 ,  H01L21/823468 ,  H01L27/11524

    Abstract: A method of fabricating a semiconductor device includes the following steps. At least a first gate stack layer and at least a second gate stack layer protruding from a conductive layer on a substrate are provided. Subsequently, two spacers and a protective layer are formed on the conductive layer, and the two spacers and the protective layer jointly surround the protruded first gate stack layer and the protruded second gate stack layer. The two spacers and the protective layer are used as a mask to remove a part of the conductive layer. Afterwards, the two spacers and the protective layer are removed.

    Abstract translation: 制造半导体器件的方法包括以下步骤。 提供至少一个第一栅堆叠层和至少一个从衬底上的导电层突出的第二栅堆叠层。 随后，在导电层上形成两个间隔物和保护层，两个间隔物和保护层共同围绕突出的第一栅叠层和突出的第二栅堆叠层。 将两个间隔物和保护层用作掩模以去除导电层的一部分。 之后，取下两个间隔物和保护层。

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