公开(公告)号：US20210273095A1

公开(公告)日：2021-09-02

申请号：US16877516

申请日：2020-05-19

Applicant: University of Electronic Science and Technology of China

Inventor： Ming QIAO ,  Longfei LIANG ,  Yilei LYU ,  Zhao QI ,  Bo Zhang

IPC: H01L29/78 ,  H01L29/66 ,  H01L21/04

Abstract: A low specific on-resistance (Ron,sp) power semiconductor device includes a power device and a transient voltage suppressor (TVS); wherein the power device comprises a gate electrode, a drain electrode, a bulk electrode, a source electrode and a parasitic body diode, the bulk electrode and the source electrode are shorted, the TVS comprises an anode electrode and a cathode electrode, the drain electrode of the power device and the anode electrode of the TVS are connected by a first metal to form a high-voltage terminal electrode, the source electrode of the power device and the cathode electrode of the TVS are connected by a second metal to form a low-voltage terminal electrode.

公开(公告)号：US20230352576A1

公开(公告)日：2023-11-02

申请号：US17876572

申请日：2022-07-29

Applicant: University of Electronic Science and Technology of China ,  Institute of Electronic and Information Engineering of UESTC in Guangdong

Inventor： Ming QIAO ,  Ruidi WANG ,  Yibing WANG ,  Bo ZHANG

IPC: H01L29/40 ,  H01L29/06 ,  H01L29/78

CPC classification number: H01L29/7811 ,  H01L29/0634 ,  H01L29/405

Abstract: A termination structure of a super-junction power device has a novel polysilicon resistive field plate at the top of a termination region between a transition region and an edge of the device. By utilizing the regular distribution of potential in the field plate, an additional electric field is introduced at the top of the termination structure to limit the expansion of a non-depletion region and optimize the distribution of charges. The termination structure includes a first doping type epitaxial layer, a second doping type compensation region, a second doping type body region, a second doping type lateral connection layer, a second doping type body contact region, a first doping type source contact region, a gate oxide layer, a passivation layer, a field oxide layer, a gate electrode, a second doping type edge contact region, a polysilicon resistive field plate, a metal layer and the like.

公开(公告)号：US20230170411A1

公开(公告)日：2023-06-01

申请号：US17714176

申请日：2022-04-06

Applicant: University of Electronic Science and Technology of China

Inventor： Ming QIAO ,  Yong CHEN ,  Wenliang LIU ,  Dong FANG ,  Fabei ZHANG ,  Bo ZHANG

IPC: H01L29/78 ,  H01L29/06 ,  H01L29/10 ,  H01L29/40 ,  H01L21/265 ,  H01L21/266 ,  H01L21/761 ,  H01L29/66

CPC classification number: H01L29/7813 ,  H01L29/063 ,  H01L29/1095 ,  H01L29/407 ,  H01L21/26513 ,  H01L21/266 ,  H01L21/761 ,  H01L29/66734

Abstract: A bidirectional conduction trench gate power MOS device and a manufacturing method thereof are provided. A gate electrode, a source electrode and a drain electrode are formed on a surface of a silicon wafer to realize a bidirectional conduction and bidirectional blocking power MOS device used in an application environment such as lithium battery BMS protection. A device structure of the bidirectional conduction trench gate power MOS device has advantages compared with double-transistor series connection used in a conventional BMS and other structures for realizing a bidirectional conduction: firstly, the bidirectional conduction trench gate power MOS device needs to occupy half or less area compared with a conventional mode, improving a degree of integration; secondly, the device structure has a simple manufacturing process and a low manufacturing cost reducing manufacturing problems; thirdly, the drain electrode and the source electrode of the device structure are exchanged to realize a symmetrical structure.

公开(公告)号：US20230129440A1

公开(公告)日：2023-04-27

申请号：US17831454

申请日：2022-06-03

Applicant: University of Electronic Science and Technology of China ,  Institute of Electronic and Information Engineering of UESTC in Guangdong

Inventor： Ming QIAO ,  Ruidi WANG ,  Yibing WANG ,  Wenyang BAI ,  Bo ZHANG

IPC: H01L29/06 ,  H01L29/10 ,  H01L29/78 ,  H01L21/265 ,  H01L21/266 ,  H01L21/761 ,  H01L29/66

Abstract: A method for manufacturing a semiconductor device is provided. A drift region and a compensation region are formed through a deep trench etching and a filling technology. A plurality of modulation doping regions are formed at a top of the drift region by an epitaxy and an ion implantation. A modulation region is introduced, wherein the modulation region flexibly modifies capacitance characteristics and achieve improved dynamic characteristics.

公开(公告)号：US20230053369A1

公开(公告)日：2023-02-23

申请号：US17744779

申请日：2022-05-16

Applicant: University of Electronic Science and Technology of China

Inventor： Wentong ZHANG ,  Ning TANG ,  Ke ZHANG ,  Nailong HE ,  Ming QIAO ,  Zhaoji LI ,  Bo ZHANG

IPC: H01L29/06 ,  H01L29/40 ,  H01L29/739 ,  H01L29/66 ,  H01L29/78

Abstract: An SOI lateral homogenization field high voltage power semiconductor device, and a manufacturing method and application thereof are provided. The device includes a type I conductive semiconductor substrate, a type II conductive drift region, a type I field clamped layer, type I and type II conductive well regions, the first dielectric oxide layer forming a field oxide layer, the second dielectric oxide layer forming a gate oxide layer, a type II conductive buried dielectric layer, a type II conductive source heavily doped region, a type II conductive drain heavily doped region. The first dielectric oxide layer and the floating field plate polysilicon electrodes form a vertical floating field plate distributed throughout the type II conductive drift region to form a vertical floating equipotential field plate array. When the device is in on-state, high doping concentration can be realized by the full-region depletion effect form the vertical field plate arrays.

公开(公告)号：US20200066714A1

公开(公告)日：2020-02-27

申请号：US16255851

申请日：2019-01-24

Applicant: University of Electronic Science and Technology of China

Inventor： Ming QIAO ,  Song PU ,  Bo ZHANG

IPC: H01L27/06 ,  H01L21/784 ,  H01L21/8258

Abstract: A BIPOLAR-CMOS-DMOS (BCD) semiconductor device and manufacturing method, which can integrate a Junction Field-Effect Transistor (JFET), two classes of Vertical Double-diffusion Metal Oxide Semiconductor (VDMOS), a Lateral Insulated-Gate Bipolar Transistor (LIGBT) and seven kinds of Laterally Diffused Metal Oxide Semiconductor (LDMOS), a low-voltage Negative channel Metal Oxide Semiconductor (NMOS), a low-voltage Positive channel Metal Oxide Semiconductor (PMOS), a low-voltage Negative-Positive-Negative (NPN) transistor and a low-voltage Positive-Negative-Positive (PNP) transistor, and a diode in the same chip. Bipolar devices in the analog circuit, power components in the switch circuit, Complementary Metal Oxide Semiconductor (CMOS) devices in the logic circuit and other kinds of lateral and vertical components are integrated. This present invention saves costs at the same time greatly improve chip integration. The manufacturing method of the present invention is simple, and the difficulty of process is relatively less.

公开(公告)号：US20190237576A1

公开(公告)日：2019-08-01

申请号：US15955706

申请日：2018-04-18

Applicant: University of Electronic Science and Technology of China

Inventor： Ming QIAO ,  Zhengkang WANG ,  Ruidi WANG ,  Zhao QI ,  Bo ZHANG

IPC: H01L29/78 ,  H01L29/423 ,  H01L29/40 ,  H01L29/08

CPC classification number: H01L29/7813 ,  H01L29/063 ,  H01L29/0649 ,  H01L29/0852 ,  H01L29/402 ,  H01L29/4236 ,  H01L29/42372 ,  H01L29/7825 ,  H01L29/7833

Abstract: A power semiconductor device including a first conductivity type semiconductor substrate, a drain metal electrode, a first conductivity type semiconductor drift region, and a second conductivity type semiconductor body region. The second conductivity type semiconductor body region includes a first conductivity type semiconductor source region and anti-punch-through structure; the anti-punch-through structure is a second conductivity type semiconductor body contact region or metal structure; the lower surface of the anti-punch-through structure coincides with the upper surface of the first conductivity type semiconductor drift region or the distance between the two is less than 0.5 μm, so that make the device avoid from punch-through. An anti-punch-through structure is introduced at the source end of the device to avoid punch-through breakdown caused by short channel and light-doped body region.