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公开(公告)号:US20230229538A1
公开(公告)日:2023-07-20
申请号:US17577627
申请日:2022-01-18
Applicant: VMware, Inc.
Inventor: Andrei Warkentin , Sunil Kotian , Jared McNeill , Shruthi Hiriyuru , Alexander Fainkichen
CPC classification number: G06F11/0757 , G06F11/0772 , G06F11/1417 , G06F11/1484 , G06F9/45541
Abstract: A hardware-assisted paravirtualized hardware watchdog is described that is used to detect and recover from computer malfunctions. A computing device determines that a hardware-implemented watchdog of the computing device does not comply with predetermined watchdog criteria, where the hardware-implemented watchdog is configured to send a reset signal when a first predetermined amount of time elapses without receipt of a first refresh signal. If the hardware-implemented watchdog does not comply with the predetermined watchdog criteria, a runtime watchdog service is initialized using a second predetermined amount of time. The runtime watchdog service is directed to periodically send the refresh signal to the hardware-implemented watchdog before an expiration of the first predetermined amount of time that causes the hardware-implemented watchdog to expire. The hardware-implemented watchdog is directed to send the reset signal when the second predetermined amount of time elapses without receipt of a second refresh signal.
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12.
公开(公告)号:US20220214968A1
公开(公告)日:2022-07-07
申请号:US17142980
申请日:2021-01-06
Applicant: VMware, Inc.
Inventor: Andrei Warkentin , Alexander Fainkichen , Ye Li , Regis Duchesne , Cyprien Laplace , Shruthi Hiriyuru , Sunil Kotian
Abstract: Techniques for enabling efficient guest OS access to PCIe configuration space are provided. In one set of embodiments, a hypervisor can reserve a single host physical memory page in the host physical memory of a host system and can populate the single host physical memory page with a value indicating non-presence of PCIe device functions. The hypervisor can then create, for each guest physical memory page in a guest physical memory of a virtual machine (VM) corresponding to a PCIe configuration space of an absent PCIe device function in the VM, a mapping in the hypervisor's second-level page tables that maps the guest physical memory page to the single host physical memory page.
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公开(公告)号:US20230325224A1
公开(公告)日:2023-10-12
申请号:US17716087
申请日:2022-04-08
Applicant: VMware, Inc.
Inventor: Andrei Warkentin , Sunil Kotian
IPC: G06F9/455 , G06F9/4401 , G06F9/48
CPC classification number: G06F9/45558 , G06F9/4401 , G06F2009/45583 , G06F2009/45595 , G06F9/4893
Abstract: Disclosed are various examples of loading management hypervisors from a system control processor. In some examples, a host device executes a first stage bootloader of a management hypervisor from a system control processor. The first stage bootloader loads management hypervisor data and firmware instructions into a main processor memory of a main processor, and initializes the main processor to execute the firmware instructions. The system then jumps to a second stage bootloader that configures and launches the management hypervisor using the management hypervisor data.
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公开(公告)号:US20230325222A1
公开(公告)日:2023-10-12
申请号:US17715292
申请日:2022-04-07
Applicant: VMware, Inc.
Inventor: Andrei Warkentin , Sunil Kotian , Ye Li , Cyprien Laplace , Regis Duchesne , Alexander Fainkichen , Shruthi Hiriyuru
IPC: G06F9/455
CPC classification number: G06F9/45558 , G06F2009/4557 , G06F2009/45595
Abstract: Disclosed are various examples of lifecycle and recovery management for virtualized data processing unit (DPU) management operating systems. A DPU device executes a DPU management hypervisor that communicates with a management service over a network. The DPU management hypervisor virtualizes DPU hardware resources and passes control of the virtualized DPU hardware resources to a DPU management operating system (OS) virtual machine (VM). The DPU management hypervisor maintains control of a management network interface card (NIC) of the DPU device.
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公开(公告)号:US20230237010A1
公开(公告)日:2023-07-27
申请号:US17580866
申请日:2022-01-21
Applicant: VMware, Inc.
Inventor: Regis Duchesne , Andrei Warkentin , Cyprien Laplace , Ye Li , Alexander Fainkichen , Shruthi Hiriyuru , Sunil Kotian
CPC classification number: G06F15/7842 , G06F9/30123
Abstract: Disclosed are various examples of providing provide efficient waiting for detection of memory value updates for Advanced RISC Machines (ARM) architectures. An ARM processor component instructs a memory agent to perform a processing action, and executes a waiting function. The waiting function ensures that the processing action is completed by the memory agent. The waiting function performs an exclusive load at a memory location, and a wait for event (WFE) instruction that causes the ARM processor component to wait in a low-power mode for an event register to be set. Once the event register is set, the waiting function completes and a second processing action is executed by the ARM processor component.
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公开(公告)号:US20230236916A1
公开(公告)日:2023-07-27
申请号:US17582055
申请日:2022-01-24
Applicant: VMware, Inc.
Inventor: Andrei Warkentin , Sunil Kotian , Jared McNeill , Cyprien Laplace , Shruthi Hiriyuru
CPC classification number: G06F11/0772 , G06F11/0778 , G06F11/0793 , G06F11/2284 , G06F11/24
Abstract: A combined data processing unit (DPU) and server solution with DPU operating system (OS) integration is described. A DPU OS is executed on a DPU or other computing device, where the DPU OS exercises secure calls provided by a DPU's trusted firmware component, that may be invoked by DPU OS components to abstract DPU vendor-specific and server vendor-specific integration details. An invocation of one of the secure calls made on the DPU to communicate with its associated server computing device is identified. In an instance in which the one of the secure calls is invoked, the secure call invoked is translated into a call or request specific to an architecture of the server computing device and the call is performed, which may include sending a signal to the server computing device in a format interpretable by the server computing device.
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17.
公开(公告)号:US20230122654A1
公开(公告)日:2023-04-20
申请号:US18069851
申请日:2022-12-21
Applicant: VMware, Inc.
Inventor: Andrei Warkentin , Alexander Fainkichen , Ye Li , Regis Duchesne , Cyprien Laplace , Shruthi Hiriyuru , Sunil Kotian
Abstract: Techniques for enabling efficient guest OS access to PCIe configuration space are provided. In one set of embodiments, a hypervisor can reserve a single host physical memory page in the host physical memory of a host system and can populate the single host physical memory page with a value indicating non-presence of PCIe device functions. The hypervisor can then create, for each guest physical memory page in a guest physical memory of a virtual machine (VM) corresponding to a PCIe configuration space of an absent PCIe device function in the VM, a mapping in the hypervisor's second-level page tables that maps the guest physical memory page to the single host physical memory page.
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公开(公告)号:US12175257B2
公开(公告)日:2024-12-24
申请号:US17715288
申请日:2022-04-07
Applicant: VMware, Inc.
Inventor: Andrei Warkentin , Sunil Kotian
IPC: G06F9/4401
Abstract: Disclosed are various examples of provisioning a data processing unit (DPU) management operating system (OS). A host device boots a host provisioning image, which executes a host provisioning agent. The host provisioning agent launches a server component that serves a DPU management OS. A provisioning command is transmitted to a DPU device installed to the host device. The server component transmits the DPU management OS from the host device to the DPU device. A host OS is executed once an indication that the DPU device is executing on the DPU management OS is received.
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公开(公告)号:US11803304B2
公开(公告)日:2023-10-31
申请号:US17578680
申请日:2022-01-19
Applicant: VMware, Inc.
Inventor: Andrei Warkentin , Sunil Kotian
CPC classification number: G06F3/0608 , G06F3/0655 , G06F3/0679 , G06F9/45558 , G06F2009/45583
Abstract: Disclosed are various examples of providing efficient bit compression for direct mapping of physical memory addresses. In some examples, a hypervisor operating system component generates a mask of used address space bits indicated by memory map entries for a computing device. A longest range of unused address space bits is identified using the mask. The memory map entries are transformed to omit the longest range of unused address space bits.
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公开(公告)号:US11741021B2
公开(公告)日:2023-08-29
申请号:US17577584
申请日:2022-01-18
Applicant: VMware, Inc.
Inventor: Srihari Venkatesan , Sunil Kotian , Andrei Warkentin , Kalaiselvi Sengottuvel
CPC classification number: G06F12/145 , G06F9/45558 , G06F12/0238 , G06F12/109 , G06F12/1433 , G06F13/4221 , G06F2009/45583 , G06F2009/45587
Abstract: Disclosed are various embodiments for various approaches for implementing trust domains to provide boundaries between PCIe devices connected to the same PCIe switch. A first trust identifier can be assigned to a first virtual machine hosted by the computing device. The first trust identifier can also be assigned to a first PCIe device assigned to the first virtual machine. Later, it can be determined that a second PCIe device connected to the PCIe switch is assigned a second trust identifier assigned to a second virtual machine. An Address Control Services (ACS) direct translated bit for peer-to-peer memory requests in the PCIe switch can be disabled in response to a determination that the second PCIe device is associated with the second trust identifier assigned to the second virtual machine.
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