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公开(公告)号：US09658878B2
公开(公告)日：2017-05-23
申请号：US14467974
申请日：2014-08-25
Applicant: VMware, Inc.
Inventor： Daniel R. K. Ports , Xiaoxin Chen , Carl A. Waldspurger , Pratap Subrahmanyam , Tal Garfinkel
CPC classification number: G06F9/461 , G06F9/4486 , G06F9/45533 , G06F9/45558 , G06F9/4881 , G06F11/1451 , G06F11/1484 , G06F2009/45562 , G06F2009/45583 , G06F2201/815 , G06F2201/84
Abstract: A virtual-machine-based system provides a mechanism to implement application file I/O operations of protected data by implementing the I/O operations semantics in a shim layer with memory-mapped regions. The semantics of these I/O operations are emulated in a shim layer with memory-mapped regions by using a mapping between a process' address space and a file or shared memory object. Data that is protected from viewing by a guest OS running in a virtual machine may nonetheless be accessed by the process.
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公开(公告)号：US11880309B2
公开(公告)日：2024-01-23
申请号：US17355941
申请日：2021-06-23
Applicant: VMware, Inc.
Inventor： Nishchay Dua , Andreas Nowatzyk , Isam Wadih Akkawi , Pratap Subrahmanyam , Venkata Subhash Reddy Peddamallu , Adarsh Seethanadi Nayak
IPC: G06F12/0897 , G06F12/0831 , G06F12/0862
CPC classification number: G06F12/0897 , G06F12/0833 , G06F12/0862 , G06F2212/152
Abstract: The state of cache lines transferred into an out of caches of processing hardware is tracked by monitoring hardware. The method of tracking includes monitoring the processing hardware for cache coherence events on a coherence interconnect between the processing hardware and monitoring hardware, determining that the state of a cache line has changed, and updating a hierarchical data structure to indicate the change in the state of said cache line. The hierarchical data structure includes a first level data structure including first bits, and a second level data structure including second bits, each of the first bits associated with a group of second bits. The step of updating includes setting one of the first bits and one of the second bits in the group corresponding to the first bit that is being set, according to an address of said cache line.
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公开(公告)号：US11782832B2
公开(公告)日：2023-10-10
申请号：US17411792
申请日：2021-08-25
Applicant: VMware, Inc.
Inventor： Isam Wadih Akkawi , Andreas Nowatzyk , Pratap Subrahmanyam , Nishchay Dua , Adarsh Seethanadi Nayak , Venkata Subhash Reddy Peddamallu , Irina Calciu
IPC: G06F13/16 , G06F13/40 , G06F12/08 , G06F12/0804
CPC classification number: G06F12/0804 , G06F13/1668 , G06F13/4027 , G06F2212/1024 , G06F2212/1032
Abstract: In a computer system, a processor and an I/O device controller communicate with each other via a coherence interconnect and according to a cache coherence protocol. Registers of the I/O device controllers are mapped to the cache coherent memory space to allow the processor to treat the registers as cacheable memory. As a result, latency of processor commands executed by the I/O device controller is decreased, and size of data stored in the I/O device controller that can be accessed by the processor is increased from the size of a single register to the size of an entire cache line.
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公开(公告)号：US11442865B1
公开(公告)日：2022-09-13
申请号：US17367078
申请日：2021-07-02
Applicant: VMware, Inc.
Inventor： Irina Calciu , Andreas Nowatzyk , Isam Wadih Akkawi , Venkata Subhash Reddy Peddamallu , Pratap Subrahmanyam
IPC: G06F12/0862
Abstract: A method of prefetching memory pages from remote memory includes detecting that a cache-line access made by a processor executing an application program is an access to a cache line containing page table data of the application program, identifying data pages that are referenced by the page table data, initiating a fetch of a data page, which is one of the identified data pages, and starting a timer. If the fetch completes prior to expiration of the timer, the data page is stored in a local memory. On the other hand, if the fetch does not complete prior to expiration of timer, a presence bit of the data page in the page table data is set to indicate that the data page is not present.
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公开(公告)号：US11163656B2
公开(公告)日：2021-11-02
申请号：US16584857
申请日：2019-09-26
Applicant: VMware, Inc.
Inventor： Pratap Subrahmanyam , Rajesh Venkatasubramanian , Kiran Tati , Qasim Ali
Abstract: Techniques for implementing high availability for persistent memory are provided. In one embodiment, a first computer system can detect an alternating current (AC) power loss/cycle event and, in response to the event, can save data in a persistent memory of the first computer system to a memory or storage device that is remote from the first computer system and is accessible by a second computer system. The first computer system can then generate a signal for the second computer system subsequently to initiating or completing the save process, thereby allowing the second computer system to restore the saved data from the memory or storage device into its own persistent memory.
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Patent Agency Ranking
公开(公告)号：US20210034600A1
公开(公告)日：2021-02-04
申请号：US17073221
申请日：2020-10-16
Applicant: VMware, Inc.
Inventor： Pratap Subrahmanyam , Zongwei Zhou , Xavier Deguillard , Rajesh Venkatasubramanian
IPC: G06F16/23
Abstract: Techniques for using commit coalescing when performing micro-journal-based transaction logging are provided. In one embodiment a computer system can maintain, in a volatile memory, a globally ascending identifier, a first list of free micro-journals, and a second list of in-flight micro-journals. The computer system can further receive a transaction comprising a plurality of modifications to data or metadata stored in the byte-addressable persistent memory, select a micro-journal from the first list, obtain a lock on the globally ascending identifier, write a current value of the globally ascending identifier as a journal commit identifier into a header of the micro-journal, and write journal entries into the micro-journal corresponding to the plurality of modifications included in the transaction. The computer system can then commit the micro-journal to the byte-addressable persistent memory, increment the current value of the globally ascending identifier, and release the lock.
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公开(公告)号：US10474550B2
公开(公告)日：2019-11-12
申请号：US15586020
申请日：2017-05-03
Applicant: VMware, Inc.
Inventor： Pratap Subrahmanyam , Rajesh Venkatasubramanian , Kiran Tati , Qasim Ali
IPC: G06F11/00 , G06F11/20 , G06F12/0804 , G06F1/30 , G06F11/14
Abstract: Techniques for implementing high availability for persistent memory are provided. In one embodiment, a first computer system can detect an alternating current (AC) power loss/cycle event and, in response to the event, can save data in a persistent memory of the first computer system to a memory or storage device that is remote from the first computer system and is accessible by a second computer system. The first computer system can then generate a signal for the second computer system subsequently to initiating or completing the save process, thereby allowing the second computer system to restore the saved data from the memory or storage device into its own persistent memory.
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公开(公告)号：US10445308B2
公开(公告)日：2019-10-15
申请号：US15192937
申请日：2016-06-24
Applicant: VMware, Inc.
Inventor： Pratap Subrahmanyam , Zongwei Zhou , Xavier Deguillard , Rajesh Venkatasubramanian
Abstract: Techniques for using commit coalescing when performing micro-journal-based transaction logging are provided. In one embodiment a computer system can maintain, in a volatile memory, a globally ascending identifier, a first list of free micro-journals, and a second list of in-flight micro-journals. The computer system can further receive a transaction comprising a plurality of modifications to data or metadata stored in the byte-addressable persistent memory, select a micro-journal from the first list, obtain a lock on the globally ascending identifier, write a current value of the globally ascending identifier as a journal commit identifier into a header of the micro-journal, and write journal entries into the micro-journal corresponding to the plurality of modifications included in the transaction. The computer system can then commit the micro-journal to the byte-addressable persistent memory, increment the current value of the globally ascending identifier, and release the lock.
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公开(公告)号：US20190129814A1
公开(公告)日：2019-05-02
申请号：US15881480
申请日：2018-01-26
Applicant: VMware, Inc.
Inventor： Kiran Tati , Qasim Ali , Wei Xu , Rajesh Venkatasubramanian , Pratap Subrahmanyam
Abstract: Techniques for implementing application fault tolerance via battery-backed replication of volatile state are provided. In one set of embodiments, a primary host system can detect a failure that causes an application of the primary host system to stop running. In response to detecting the failure, the primary host system can replicate volatile state that is used by the application to a secondary host system, where the secondary host system maintains a copy of the application, and where execution of the application is failed over to the copy on the secondary host system using the replicated volatile state.
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20.发明申请公开(公告)号：US20190129812A1
公开(公告)日：2019-05-02
申请号：US15881379
申请日：2018-01-26
Applicant: VMware, Inc.
Inventor： Pratap Subrahmanyam , Rajesh Venkatasubramanian , Kiran Tati , Qasim Ali , Marcos Aguilera , Irina Calciu , Venkata Subhash Reddy Peddamallu , Xavier Deguillard , Yi Yao
Abstract: Techniques for achieving application high availability via application-transparent battery-backed replication of persistent data are provided. In one set of embodiments, a computer system can detect a failure that causes an application of the computer system to stop running. In response to detecting the failure, the computer system can copy persistent data written by the application and maintained locally at the computer system to one or more remote destinations, where the copying is performed in a manner that is transparent to the application and while the computer system runs on battery power. The application can then be restarted on another computer system using the copied data.
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