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公开(公告)号：US20110063920A1
公开(公告)日：2011-03-17
申请号：US12561692
申请日：2009-09-17
摘要： Methods for sensing, memory devices, and memory systems are disclosed. One such method for sensing includes charging bit lines of an all bit line architecture to a precharge voltage, selecting a word line, and performing a sense operation on the bit lines. After the sense operation on the memory cells of the first selected word line is complete, the precharge voltage is maintained on the bit lines while a second word line is selected.
摘要翻译： 公开了用于感测，存储器件和存储器系统的方法。 一种用于感测的方法包括将全位线架构的位线充电到预充电电压，选择字线以及对位线进行感测操作。 在对第一选定字线的存储单元进行感测操作完成之后，在选择第二字线的同时，在位线上保持预充电电压。
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12.发明授权公开(公告)号：US07848158B2
公开(公告)日：2010-12-07
申请号：US12151265
申请日：2008-05-05
IPC分类号： G11C7/00
摘要： Methods and apparatuses for programming non-volatile semiconductor memory devices by using modulated pulses are disclosed. An apparatus may have a pulse generator, to create a sequence of pulses and set a threshold voltage of a non-volatile memory cell, and a pulse coupler. The apparatus may have a threshold verifier capable of verifying that the threshold voltage is set within an acceptable voltage range of a target threshold voltage. A pulse width modulator in some apparatuses may modulate the pulse durations early in the sequence when programming fast bits and late in the sequence when programming slow bits. An apparatus may generate a sequence of pulses, apply the sequence of pulses to a memory cell to set a threshold voltage of the memory cell, and modulate one or more of pulses in the sequence the parameters of pulse duration, pulse separation time, and step voltage magnitude.
摘要翻译： 公开了通过使用调制脉冲来编程非易失性半导体存储器件的方法和装置。 装置可以具有脉冲发生器，以产生脉冲序列并设置非易失性存储单元的阈值电压和脉冲耦合器。 该装置可以具有能够验证阈值电压被设置在目标阈值电压的可接受电压范围内的阈值校验器。 某些设备中的脉冲宽度调制器可以在编程快速位时在序列的早期调制脉冲持续时间，而在编程慢位时可以在序列的后期调制脉冲持续时间。 设备可以产生脉冲序列，将脉冲序列应用于存储器单元以设置存储器单元的阈值电压，并且调制脉冲持续时间，脉冲间隔时间和步长的参数中的一个或多个脉冲 电压幅度。
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13.发明授权公开(公告)号：US07639534B2
公开(公告)日：2009-12-29
申请号：US11860949
申请日：2007-09-25
CPC分类号： G11C16/0483 , G11C16/24 , G11C16/26
摘要： Device, system, and method of bit line selection of a flash memory. In some demonstrative embodiments, the method may include connecting to ground at least one location along at least one bit line of a flash memory when the bit line is at an unselected state, wherein the bit line is connected to a multiplexer, and wherein at least one memory sector is coupled to the bit line between the multiplexer and the location; and connecting the location to a precharge path when the bit line is at a selected state.
摘要翻译： Flash存储器的位线选择的设备，系统和方法。 在一些说明性实施例中，当位线处于未选择状态时，该方法可以包括沿闪速存储器的至少一个位线的至少一个位置连接到地，其中位线连接到多路复用器，并且其中至少 一个存储器扇区耦合到多路复用器和位置之间的位线; 以及当所述位线处于选定状态时将所述位置连接到预充电路径。
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公开(公告)号：US20080239806A1
公开(公告)日：2008-10-02
申请号：US12038445
申请日：2008-02-27
CPC分类号： G11C11/5628 , G11C16/0483 , G11C16/3404 , G11C16/3486 , G11C2211/5621 , G11C2211/5625
摘要： Embodiments of the present disclosure provide methods, devices, modules, and systems for programming multilevel non-volatile multilevel memory cells. One method includes increasing a threshold voltage (Vt) for each of a number of memory cells until the Vt reaches a verify voltage (VFY) corresponding to a program state among a number of program states. The method includes determining whether the Vt of each of the cells has reached a pre-verify voltage (PVFY) associated with the program state, selectively biasing bit lines coupled to those cells whose Vt has reached the PVFY, adjusting the PVFY to a different level, and selectively biasing bit lines coupled to cells whose Vt has reached the adjusted PVFY, wherein the PVFY and the adjusted PVFY are less than the VFY.
摘要翻译： 本公开的实施例提供用于编程多电平非易失性多电平存储器单元的方法，设备，模块和系统。 一种方法包括增加用于多个存储器单元中的每一个的阈值电压（Vt），直到Vt达到与多个程序状态中的程序状态相对应的验证电压（VFY）。 该方法包括确定每个单元的Vt是否已经达到与编程状态相关联的预验证电压（PVFY），选择性地偏置与Vt已经达到PVFY的那些单元耦合的位线，将PVFY调整到不同的水平 并且选择性地偏置与Vt已经达到调整后的PVFY的单元相连的位线，其中PVFY和调整后的PVFY小于VFY。
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公开(公告)号：US08902648B2
公开(公告)日：2014-12-02
申请号：US13190911
申请日：2011-07-26
CPC分类号： G11C16/3436 , G11C11/5628 , G11C16/10 , G11C16/26 , G11C16/34 , G11C16/3418 , G11C16/3422
摘要： Methods for determining a program window and memory devices are disclosed. One such method for determining the program window measures an amount of program disturb experienced by a particular state and determines the program window responsive to the amount of program disturb.
摘要翻译： 公开了用于确定程序窗口和存储器件的方法。 用于确定程序窗口的一种这样的方法测量由特定状态经历的程序干扰量，并且响应于程序干扰量确定程序窗口。
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公开(公告)号：US20120287726A1
公开(公告)日：2012-11-15
申请号：US13561248
申请日：2012-07-30
IPC分类号： G11C7/00
CPC分类号： G11C16/3427 , G11C11/5628 , G11C16/10 , G11C16/3418 , G11C27/02 , G11C2211/5642 , G11C2211/5646
摘要： Methods of programming a memory, memory devices, and systems are disclosed, for example. In one such method, each data line of a memory to be programmed is biased differently depending upon whether one or more of the data lines adjacent the data line are inhibited. In one such system, a connection circuit provides data corresponding to the inhibit status of a target data line to page buffers associated with data lines adjacent to the target data line.
摘要翻译： 例如，公开了存储器，存储器件和系统的编程方法。 在一种这样的方法中，根据是否禁止与数据线相邻的一条或多条数据线，要编程的存储器的每条数据线被不同地偏置。 在一个这样的系统中，连接电路将对应于目标数据线的禁止状态的数据提供给与与目标数据线相邻的数据线相关联的寻呼缓冲器。
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公开(公告)号：US20120262993A1
公开(公告)日：2012-10-18
申请号：US13085611
申请日：2011-04-13
CPC分类号： G11C16/0483 , G11C16/26
摘要： Methods of operating memory devices, generating reference currents in memory devices, and sensing data states of memory cells in a memory device are disclosed. One such method includes generating reference currents utilized in sense amplifier circuitry to manage leakage currents while performing a sense operation within a memory device. Another such method activates one of two serially coupled transistors along with activating and deactivating the second transistor serially coupled with the first transistor thereby regulating a current through both serially coupled transistors and establishing a particular reference current.
摘要翻译： 公开了在存储器件中操作存储器件，产生存储器件中的参考电流以及感测存储器单元的数据状态的方法。 一种这样的方法包括产生在读出放大器电路中使用的参考电流，以在存储器件内进行感测操作的同时管理泄漏电流。 另一种这样的方法激活两个串联耦合晶体管中的一个，同时激活和去激活与第一晶体管串联耦合的第二晶体管，从而调节通过两个串联耦合的晶体管的电流并建立特定的参考电流。
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公开(公告)号：US08169830B2
公开(公告)日：2012-05-01
申请号：US12561692
申请日：2009-09-17
IPC分类号： G11C16/06
摘要： Methods for sensing, memory devices, and memory systems are disclosed. One such method for sensing includes charging bit lines of an all bit line architecture to a precharge voltage, selecting a word line, and performing a sense operation on the bit lines. After the sense operation on the memory cells of the first selected word line is complete, the precharge voltage is maintained on the bit lines while a second word line is selected.
摘要翻译： 公开了用于感测，存储器件和存储器系统的方法。 一种用于感测的方法包括将全位线架构的位线充电到预充电电压，选择字线以及对位线进行感测操作。 在对第一选定字线的存储单元进行感测操作完成之后，在选择第二字线的同时，在位线上保持预充电电压。
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公开(公告)号：US20100091582A1
公开(公告)日：2010-04-15
申请号：US12365589
申请日：2009-02-04
CPC分类号： G11C16/3427 , G11C11/5628 , G11C16/10 , G11C16/3418 , G11C27/02 , G11C2211/5642 , G11C2211/5646
摘要： Methods of programming a memory, memory devices, and systems are disclosed, for example. In one such method, each data line of a memory to be programmed is biased differently depending upon whether one or more of the data lines adjacent the data line are inhibited. In one such system, a connection circuit provides data corresponding to the inhibit status of a target data line to page buffers associated with data lines adjacent to the target data line.
摘要翻译： 例如，公开了存储器，存储器件和系统的编程方法。 在一种这样的方法中，根据是否禁止与数据线相邻的一条或多条数据线，要编程的存储器的每条数据线被不同地偏置。 在一个这样的系统中，连接电路将对应于目标数据线的禁止状态的数据提供给与与目标数据线相邻的数据线相关联的寻呼缓冲器。
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公开(公告)号：US07692971B2
公开(公告)日：2010-04-06
申请号：US12038445
申请日：2008-02-27
IPC分类号： G11C11/34
CPC分类号： G11C11/5628 , G11C16/0483 , G11C16/3404 , G11C16/3486 , G11C2211/5621 , G11C2211/5625
摘要： Embodiments of the present disclosure provide methods, devices, modules, and systems for programming multilevel non-volatile multilevel memory cells. One method includes increasing a threshold voltage (Vt) for each of a number of memory cells until the Vt reaches a verify voltage (VFY) corresponding to a program state among a number of program states. The method includes determining whether the Vt of each of the cells has reached a pre-verify voltage (PVFY) associated with the program state, selectively biasing bit lines coupled to those cells whose Vt has reached the PVFY, adjusting the PVFY to a different level, and selectively biasing bit lines coupled to cells whose Vt has reached the adjusted PVFY, wherein the PVFY and the adjusted PVFY are less than the VFY.
摘要翻译： 本公开的实施例提供用于编程多电平非易失性多电平存储器单元的方法，设备，模块和系统。 一种方法包括增加用于多个存储器单元中的每一个的阈值电压（Vt），直到Vt达到与多个程序状态中的程序状态相对应的验证电压（VFY）。 该方法包括确定每个单元的Vt是否已经达到与编程状态相关联的预验证电压（PVFY），选择性地偏置与Vt已经达到PVFY的那些单元耦合的位线，将PVFY调整到不同的水平 并且选择性地偏置与Vt已经达到调整后的PVFY的单元相连的位线，其中PVFY和调整后的PVFY小于VFY。
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