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1.发明申请公开(公告)号：US20090273981A1
公开(公告)日：2009-11-05
申请号：US12151265
申请日：2008-05-05
IPC分类号： G11C16/12
摘要： Methods and apparatuses for programming non-volatile semiconductor memory devices by using modulated pulses are disclosed. Embodiments generally comprise a pulse generator, to create a sequence of pulses and set a threshold voltage of a non-volatile memory cell, and a pulse coupler. Alternative embodiments may include a threshold verifier capable of verifying that the threshold voltage is set within an acceptable voltage range of a target threshold voltage. A pulse width modulator in some apparatus embodiments may modulate the pulse durations early in the sequence when programming fast bits and late in the sequence when programming slow bits. Method embodiments generally comprise generating a sequence of pulses, applying the sequence of pulses to a memory cell to set a threshold voltage of the memory cell, and modulating among pulses in the sequence the parameters of pulse duration, pulse separation time, and step voltage magnitude.
摘要翻译： 公开了通过使用调制脉冲来编程非易失性半导体存储器件的方法和装置。 实施例通常包括脉冲发生器，以产生脉冲序列并设置非易失性存储单元的阈值电压和脉冲耦合器。 替代实施例可以包括能够验证阈值电压被设置在目标阈值电压的可接受电压范围内的阈值校验器。 某些设备实施例中的脉冲宽度调制器可以在编程快速位时在序列的早期调制脉冲持续时间，而在编程慢位时可以在序列的后期调制脉冲持续时间。 方法实施例通常包括产生脉冲序列，将脉冲序列应用于存储器单元以设置存储器单元的阈值电压，以及在该序列中的脉冲之间调制脉冲持续时间，脉冲间隔时间和步进电压幅度的参数 。
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2.发明授权公开(公告)号：US07848158B2
公开(公告)日：2010-12-07
申请号：US12151265
申请日：2008-05-05
IPC分类号： G11C7/00
摘要： Methods and apparatuses for programming non-volatile semiconductor memory devices by using modulated pulses are disclosed. An apparatus may have a pulse generator, to create a sequence of pulses and set a threshold voltage of a non-volatile memory cell, and a pulse coupler. The apparatus may have a threshold verifier capable of verifying that the threshold voltage is set within an acceptable voltage range of a target threshold voltage. A pulse width modulator in some apparatuses may modulate the pulse durations early in the sequence when programming fast bits and late in the sequence when programming slow bits. An apparatus may generate a sequence of pulses, apply the sequence of pulses to a memory cell to set a threshold voltage of the memory cell, and modulate one or more of pulses in the sequence the parameters of pulse duration, pulse separation time, and step voltage magnitude.
摘要翻译： 公开了通过使用调制脉冲来编程非易失性半导体存储器件的方法和装置。 装置可以具有脉冲发生器，以产生脉冲序列并设置非易失性存储单元的阈值电压和脉冲耦合器。 该装置可以具有能够验证阈值电压被设置在目标阈值电压的可接受电压范围内的阈值校验器。 某些设备中的脉冲宽度调制器可以在编程快速位时在序列的早期调制脉冲持续时间，而在编程慢位时可以在序列的后期调制脉冲持续时间。 设备可以产生脉冲序列，将脉冲序列应用于存储器单元以设置存储器单元的阈值电压，并且调制脉冲持续时间，脉冲间隔时间和步长的参数中的一个或多个脉冲 电压幅度。
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公开(公告)号：US08395939B2
公开(公告)日：2013-03-12
申请号：US13090754
申请日：2011-04-20
IPC分类号： G11C11/34
CPC分类号： G11C16/04 , G11C16/0483 , G11C16/06 , G11C16/10 , G11C16/26 , G11C29/76 , G11C29/789 , G11C29/82 , G11C2211/5621 , G11C2211/5642
摘要： In one or more of the disclosed embodiments, a read operation is compensated for back pattern effect. A bit line current is generated by a read operation that biases the word lines. As part of a back pattern effect measurement phase, at predetermined time intervals an indication of the discharge status of the bit line is stored in a latch of a set of N latches coupled to each bit line. At the end of the measurement phase, the set of latches contains a multiple bit word that is an indication of the back pattern effect experienced by that particular series string of memory cells. This back pattern effect indication is used in subsequent read operations to adjust the timing of the operation.
摘要翻译： 在所公开的一个或多个实施例中，读取操作被补偿以用于背面图案效果。 通过偏置字线的读取操作产生位线电流。 作为背景图案效果测量阶段的一部分，在预定的时间间隔，将位线的放电状态的指示存储在耦合到每个位线的一组N个锁存器的锁存器中。 在测量阶段结束时，锁存器组包含一个多位字，它是该特定串行存储单元所经历的反向图案效应的指示。 这种背面图案效果指示用于随后的读取操作以调整操作的时间。
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公开(公告)号：US08233329B2
公开(公告)日：2012-07-31
申请号：US12365589
申请日：2009-02-04
IPC分类号： G11C11/34
CPC分类号： G11C16/3427 , G11C11/5628 , G11C16/10 , G11C16/3418 , G11C27/02 , G11C2211/5642 , G11C2211/5646
摘要： Methods of programming a memory, memory devices, and systems are disclosed, for example. In one such method, each data line of a memory to be programmed is biased differently depending upon whether one or more of the data lines adjacent the data line are inhibited. In one such system, a connection circuit provides data corresponding to the inhibit status of a target data line to page buffers associated with data lines adjacent to the target data line.
摘要翻译： 例如，公开了存储器，存储器件和系统的编程方法。 在一种这样的方法中，根据是否禁止与数据线相邻的一条或多条数据线，要编程的存储器的每条数据线被不同地偏置。 在一个这样的系统中，连接电路将对应于目标数据线的禁止状态的数据提供给与与目标数据线相邻的数据线相关联的寻呼缓冲器。
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公开(公告)号：US08638624B2
公开(公告)日：2014-01-28
申请号：US13561248
申请日：2012-07-30
IPC分类号： G11C7/00
CPC分类号： G11C16/3427 , G11C11/5628 , G11C16/10 , G11C16/3418 , G11C27/02 , G11C2211/5642 , G11C2211/5646
摘要： Methods of programming a memory, memory devices, and systems are disclosed, for example. In one such method, each data line of a memory to be programmed is biased differently depending upon whether one or more of the data lines adjacent the data line are inhibited. In one such system, a connection circuit provides data corresponding to the inhibit status of a target data line to page buffers associated with data lines adjacent to the target data line.
摘要翻译： 例如，公开了存储器，存储器件和系统的编程方法。 在一种这样的方法中，根据是否禁止与数据线相邻的一条或多条数据线，要编程的存储器的每条数据线被不同地偏置。 在一个这样的系统中，连接电路将对应于目标数据线的禁止状态的数据提供给与与目标数据线相邻的数据线相关联的寻呼缓冲器。
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公开(公告)号：US08593876B2
公开(公告)日：2013-11-26
申请号：US13085611
申请日：2011-04-13
CPC分类号： G11C16/0483 , G11C16/26
摘要： Methods of operating memory devices, generating reference currents in memory devices, and sensing data states of memory cells in a memory device are disclosed. One such method includes generating reference currents utilized in sense amplifier circuitry to manage leakage currents while performing a sense operation within a memory device. Another such method activates one of two serially coupled transistors along with activating and deactivating the second transistor serially coupled with the first transistor thereby regulating a current through both serially coupled transistors and establishing a particular reference current.
摘要翻译： 公开了在存储器件中操作存储器件，产生存储器件中的参考电流以及感测存储器单元的数据状态的方法。 一种这样的方法包括产生在读出放大器电路中使用的参考电流，以在存储器件内进行感测操作的同时管理泄漏电流。 另一种这样的方法激活两个串联耦合晶体管中的一个，同时激活和去激活与第一晶体管串联耦合的第二晶体管，从而调节通过两个串联耦合的晶体管的电流并建立特定的参考电流。
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公开(公告)号：US08553461B2
公开(公告)日：2013-10-08
申请号：US13585389
申请日：2012-08-14
申请人： Violante Moschiano , Frankie Roohparvar , Giovanni Santin , Vishal Sarin , Allahyar Vahidimowlavi , Tommaso Vali
发明人： Violante Moschiano , Frankie Roohparvar , Giovanni Santin , Vishal Sarin , Allahyar Vahidimowlavi , Tommaso Vali
IPC分类号： G11C7/00
CPC分类号： G11C16/10 , G11C11/404 , G11C11/5628 , G11C16/3404
摘要： This disclosure concerns memory kink compensation. One method embodiment includes applying a number of sequentially incrementing programming pulses to a memory cell, with the sequential programming pulses incrementing by a first programming pulse step voltage magnitude. A seeding voltage is applied after applying the number of sequentially incrementing programming pulses. A next programming pulse is applied after applying the seeding voltage, with the next programming pulse being adjusted relative to a preceding one of the sequentially incrementing programming pulses by a second programming pulse step voltage magnitude. The second programming pulse step voltage magnitude can be less than the first programming pulse step voltage magnitude.
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公开(公告)号：US08243521B2
公开(公告)日：2012-08-14
申请号：US12631606
申请日：2009-12-04
申请人： Violante Moschiano , Frankie Roohparvar , Giovanni Santin , Vishal Sarin , Allahyar Vahidimowlavi , Tommaso Vali
发明人： Violante Moschiano , Frankie Roohparvar , Giovanni Santin , Vishal Sarin , Allahyar Vahidimowlavi , Tommaso Vali
IPC分类号： G11C16/04
CPC分类号： G11C16/10 , G11C11/404 , G11C11/5628 , G11C16/3404
摘要： This disclosure concerns memory kink compensation. One method embodiment includes applying a number of sequentially incrementing programming pulses to a memory cell, with the sequential programming pulses incrementing by a first programming pulse step voltage magnitude. A seeding voltage is applied after applying the number of sequentially incrementing programming pulses. A next programming pulse is applied after applying the seeding voltage, with the next programming pulse being adjusted relative to a preceding one of the sequentially incrementing programming pulses by a second programming pulse step voltage magnitude. The second programming pulse step voltage magnitude can be less than the first programming pulse step voltage magnitude.
摘要翻译： 本公开涉及存储器扭结补偿。 一个方法实施例包括将多个顺序递增的编程脉冲施加到存储器单元，其中顺序编程脉冲通过第一编程脉冲阶跃电压幅度递增。 在施加顺序递增的编程脉冲数之后施加接种电压。 在施加播种电压之后施加下一个编程脉冲，其中下一个编程脉冲相对于先前的一个顺序递增的编程脉冲通过第二编程脉冲阶跃电压幅度被调整。 第二个编程脉冲阶跃电压幅度可以小于第一个编程脉冲阶跃电压幅度。
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公开(公告)号：US20110134701A1
公开(公告)日：2011-06-09
申请号：US12631606
申请日：2009-12-04
申请人： Violante Moschiano , Frankie F. Roohparvar , Giovanni Santin , Vishal Sarin , Allahyar Vahidimowlavi , Tommaso Vali
发明人： Violante Moschiano , Frankie F. Roohparvar , Giovanni Santin , Vishal Sarin , Allahyar Vahidimowlavi , Tommaso Vali
IPC分类号： G11C16/12
CPC分类号： G11C16/10 , G11C11/404 , G11C11/5628 , G11C16/3404
摘要： This disclosure concerns memory kink compensation. One method embodiment includes applying a number of sequentially incrementing programming pulses to a memory cell, with the sequential programming pulses incrementing by a first programming pulse step voltage magnitude. A seeding voltage is applied after applying the number of sequentially incrementing programming pulses. A next programming pulse is applied after applying the seeding voltage, with the next programming pulse being adjusted relative to a preceding one of the sequentially incrementing programming pulses by a second programming pulse step voltage magnitude. The second programming pulse step voltage magnitude can be less than the first programming pulse step voltage magnitude.
摘要翻译： 本公开涉及存储器扭结补偿。 一个方法实施例包括将多个顺序递增的编程脉冲施加到存储器单元，其中顺序编程脉冲通过第一编程脉冲阶跃电压幅度递增。 在施加顺序递增的编程脉冲数之后施加接种电压。 在施加播种电压之后施加下一个编程脉冲，其中下一个编程脉冲相对于先前的一个顺序递增的编程脉冲通过第二编程脉冲步长电压幅度被调整。 第二个编程脉冲阶跃电压幅度可以小于第一个编程脉冲阶跃电压幅度。
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公开(公告)号：US20100165739A1
公开(公告)日：2010-07-01
申请号：US12718290
申请日：2010-03-05
IPC分类号： G11C16/04
CPC分类号： G11C11/5628 , G11C16/0483 , G11C16/3404 , G11C16/3486 , G11C2211/5621 , G11C2211/5625
摘要： Embodiments of the present disclosure provide methods, devices, modules, and systems for programming multilevel non-volatile multilevel memory cells. One method includes increasing a threshold voltage (Vt) for each of a number of memory cells until the Vt reaches a verify voltage (VFY) corresponding to a program state among a number of program states. The method includes determining whether the Vt of each of the cells has reached a pre-verify voltage (PVFY) associated with the program state, selectively biasing bit lines coupled to those cells whose Vt has reached the PVFY, adjusting the PVFY to a different level, and selectively biasing bit lines coupled to cells whose Vt has reached the adjusted PVFY, wherein the PVFY and the adjusted PVFY are less than the VFY.
摘要翻译： 本公开的实施例提供用于编程多电平非易失性多电平存储器单元的方法，设备，模块和系统。 一种方法包括增加用于多个存储器单元中的每一个的阈值电压（Vt），直到Vt达到与多个程序状态中的程序状态相对应的验证电压（VFY）。 该方法包括确定每个单元的Vt是否已经达到与编程状态相关联的预验证电压（PVFY），选择性地偏置与Vt已经达到PVFY的那些单元耦合的位线，将PVFY调整到不同的水平 并且选择性地偏置与Vt已经达到调整后的PVFY的单元相连的位线，其中PVFY和调整后的PVFY小于VFY。
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