公开(公告)号：US20070088879A1

公开(公告)日：2007-04-19

申请号：US11538693

申请日：2006-10-04

Applicant: Chung-Ching Huang ,  Ta-Chuan Liu ,  Tzu-Chiang Chiu ,  Chin-Fa Hsiao

Inventor： Chung-Ching Huang ,  Ta-Chuan Liu ,  Tzu-Chiang Chiu ,  Chin-Fa Hsiao

IPC: G06F13/12

CPC classification number: G06F13/385

Abstract: In a method used for initializing a first bus device and a second bus device sharing a common transmission engine of a bus, a first link of the first bus device and a second link of the second bus device to the common transmission engine are disabled when the computer system is booted. Next, the first link and the second link are enabled in order. Then, a first state updating signal from the first bus device is issued after the first link to the common transmission engine is established. Finally, a second state updating signal from the second bus device is issued after the first state updating signal is received and the second link to the common transmission engine is established.

Abstract translation: 在用于初始化共享总线的公共传输引擎的第一总线设备和第二总线设备的方法中，当第一总线设备的第一链路和第二总线设备的第二链路到公共传输引擎时，当第 计算机系统启动。 接下来，按顺序启用第一个链接和第二个链接。 然后，在建立到公共传输引擎的第一链路之后，发出来自第一总线设备的第一状态更新信号。 最后，在接收到第一状态更新信号并建立到公共传输引擎的第二链路之后，发出来自第二总线设备的第二状态更新信号。

公开(公告)号：US07162568B2

公开(公告)日：2007-01-09

申请号：US10757464

申请日：2004-01-15

Applicant: Chung-Ching Huang ,  Kuan-Jui Ho

Inventor： Chung-Ching Huang ,  Kuan-Jui Ho

IPC: G06F12/00

CPC classification number: G06F11/2284

Abstract: An apparatus and method of flash ROM management. The apparatus comprises a storage device, a strapping component and a process unit. The storage device stores multiple address records comprising an identity and an address range associated with a flash ROM. The strapping component is configured to output a signal to determine flash ROM type. The process unit receives a memory access request with an access range from the CPU and the signal from the strapping component queries the identity by matching the access range and the address range, and finally executes an LPC 1.1 memory access instruction with the identity and the access range corresponding to the memory cycle.

Abstract translation: 一种闪存ROM管理的设备和方法。 该装置包括存储装置，捆扎部件和处理单元。 存储设备存储包括与快闪ROM相关联的身份和地址范围的多个地址记录。 绑带组件配置为输出信号以确定闪存ROM类型。 处理单元从CPU接收具有访问范围的存储器访问请求，并且来自绑带组件的信号通过匹配访问范围和地址范围来查询身份，并且最终执行具有身份和访问权的LPC 1.1存储器访问指令 范围对应于存储器周期。

公开(公告)号：US20060031690A1

公开(公告)日：2006-02-09

申请号：US10963149

申请日：2004-10-12

Applicant: Chien-Ping Chung ,  Chung-Ching Huang ,  Jing-Rung Wang

Inventor： Chien-Ping Chung ,  Chung-Ching Huang ,  Jing-Rung Wang

IPC: G06F1/30

CPC classification number: G06F1/324 ,  G06F1/3203 ,  Y02D10/126

Abstract: A system and method for power management in computer systems. System status assessed by a Northbridge, and the result transferred to a Southbridge. A system control table is provided in the Southbridge, whereby power management without software control is provided.

Abstract translation: 计算机系统中电源管理的系统和方法。 由北桥评估的系统状态，结果转移到南桥。 在南桥提供了一个系统控制表，从而提供无需软件控制的电源管理。

公开(公告)号：US20050120154A1

公开(公告)日：2005-06-02

申请号：US11000300

申请日：2004-11-30

Applicant: Tony Ho ,  Chung-Ching Huang ,  Norman Chung

Inventor： Tony Ho ,  Chung-Ching Huang ,  Norman Chung

IPC: G06F13/24

CPC classification number: G06F13/24 ,  Y02D10/14

Abstract: An interruption control system includes an interruption message generator, a stop clock control module and an interruption status indicating path. The interruption message generator is used for decoding and identifying a message signaled interrupt (MSI) issued by a first peripheral device or a second peripheral device when interruption is to be conducted, and generates an interruption status indicating message in response to the message signaled interrupt (MSI). The stop clock control module is coupled to the interruption message generator and the CPU and de-asserts a stop clock signal that is previously asserted to have the CPU enter a power-saving state to have the CPU deactivate the power-saving state in response to the interruption status indicating message. The interruption status indicating path is used for transmitting the interruption status indicating message.

Abstract translation: 中断控制系统包括中断消息发生器，停止时钟控制模块和中断状态指示路径。 所述中断消息发生器用于在进行中断时解码和识别由第一外围设备或第二外围设备发出的消息信号中断（MSI），并响应于消息信号中断产生中断状态指示消息（ MSI）。 停止时钟控制模块耦合到中断消息发生器和CPU，并且取消断言先前断言的停止时钟信号，以使CPU进入省电状态，以使CPU能够响应于CPU 中断状态指示消息。 中断状态指示路径用于发送中断状态指示消息。

公开(公告)号：US20050114723A1

公开(公告)日：2005-05-26

申请号：US10980443

申请日：2004-11-03

Applicant: Tony Ho ,  Chung-Ching Huang ,  Norman Chung

Inventor： Tony Ho ,  Chung-Ching Huang ,  Norman Chung

IPC: G06F1/32 ,  G06F1/26

CPC classification number: G06F1/3215

Abstract: An interruption control system includes a first input/output interruption controller, a second input/output interruption controller and an interruption status indicating path. The first input/output interruption controller is coupled to a first peripheral device and a south bridge chip, and issues a wake-up signal to the south bridge chip in response to a first interrupt signal asserted by the first peripheral device so as to deactivate a power-saving state of the computer system. The second input/output interruption controller is coupled to a second peripheral device and a north bridge chip, and in response to a second interrupt signal asserted by the second peripheral device, generates a message signaled interrupt. The interruption status indicating path transmits the message signaled interrupt from the second input/output interruption controller to the south bridge chip to have the south bridge chip deactivate the power-saving state of the computer system in response to the message signaled interrupt.

Abstract translation: 中断控制系统包括第一输入/输出中断控制器，第二输入/输出中断控制器和中断状态指示路径。 第一输入/输出中断控制器耦合到第一外围设备和南桥芯片，并且响应于由第一外围设备断言的第一中断信号向南桥芯片发出唤醒信号， 计算机系统的省电状态。 第二输入/输出中断控制器耦合到第二外围设备和北桥芯片，并且响应于由第二外围设备断言的第二中断信号，产生消息信号中断。 中断状态指示路径将消息信号中断从第二输入/输出中断控制器发送到南桥芯片，以使南桥芯片响应于消息信号中断而使计算机系统的省电状态停止。

公开(公告)号：US20120137038A1

公开(公告)日：2012-05-31

申请号：US13184345

申请日：2011-07-15

Applicant: Chung-Ching Huang ,  Yeh Cho ,  Donna Lim

Inventor： Chung-Ching Huang ,  Yeh Cho ,  Donna Lim

IPC: G06F13/14

CPC classification number: G06F1/324 ,  G06F1/1632 ,  Y02D10/126

Abstract: Electronic systems supporting multiple operation modes are provided, wherein the electronic system includes a portable device and a docking system. The portable device at least includes one processing unit and a first operation module, wherein the processing unit includes a plurality of operation frequencies and is operable in a plurality of operation modes, and each operation mode corresponds to an operation frequency. The docking system includes a container for containing the portable device and a second operation module. When the portable device is plugged into the container of the docking system, the portable device receives a signal from the docking system, determines an operation mode of the portable device according to the received signal, adjusts the operation frequency of the processing unit corresponding to the operation mode and selectively applies the first modules or second modules to control the electronic system.

Abstract translation: 提供了支持多种操作模式的电子系统，其中电子系统包括便携式设备和对接系统。 便携式设备至少包括一个处理单元和第一操作模块，其中处理单元包括多个操作频率并且可以在多个操作模式中操作，并且每个操作模式对应于操作频率。 对接系统包括用于容纳便携式设备的容器和第二操作模块。 当便携式设备插入到对接系统的容器中时，便携式设备从对接系统接收信号，根据接收到的信号确定便携式设备的操作模式，调整对应于该接收信号的处理单元的操作频率 并且选择性地应用第一模块或第二模块来控制电子系统。

公开(公告)号：US07716533B2

公开(公告)日：2010-05-11

申请号：US11656455

申请日：2007-01-23

Applicant: Chung-Ching Huang ,  Chien-Ping Chung ,  Yeh Cho

Inventor： Chung-Ching Huang ,  Chien-Ping Chung ,  Yeh Cho

IPC: G06F11/00

CPC classification number: G06F11/221

Abstract: A bus cycle trapping system includes at least one register, a north bridge, a south bridge and a central processing unit (CPU). The register is configured to store at least one trapping parameter. The north bridge traps a bus cycle matching the at least one trapping parameter while issuing an activating signal. The south bridge sends a system management interrupt message according to the activating signal. The CPU enters a system management mode according to the system management interrupt and executes a system management interrupt routine for doing a debugging test of the bus cycle matching the trapping parameter.

Abstract translation: 总线周期捕集系统包括至少一个寄存器，北桥，南桥和中央处理单元（CPU）。 寄存器被配置为存储至少一个捕获参数。 北桥在发出激活信号的同时捕获与至少一个捕获参数匹配的总线周期。 南桥根据激活信号发送系统管理中断消息。 CPU根据系统管理中断进入系统管理模式，执行系统管理中断程序，进行与捕获参数匹配的总线周期的调试测试。

公开(公告)号：US07296185B2

公开(公告)日：2007-11-13

申请号：US10820768

申请日：2004-04-09

Applicant: Chung-Ching Huang ,  Hao-Lin Lin

Inventor： Chung-Ching Huang ,  Hao-Lin Lin

IPC: G06F11/00

CPC classification number: G06F11/362

Abstract: A debugging device and method are provided, including a central processing unit (CPU) connected to a chipset with a system management interrupt pin. The debugging method includes sending out a system management interrupt signal to central processing unit from the system management interrupt pin of the chipset. Then the CPU moves into a system management mode and pops out a debugging operation window for selecting and executing each debugging item. After the execution of each debugging item is completed, the CPU will leave the debugging operation window and return to the next instruction before debugging. After the execution of each debugging item is completed in the debugging operation window, the CPU will return to the operation system and continue the execution of next instruction before debugging. The execution of debugging will not influence the status and the program execution from the operating system. The disclosed debugging method is convenient for executing each debugging item at any time.

Abstract translation: 提供了一种调试设备和方法，包括连接到具有系统管理中断引脚的芯片组的中央处理单元（CPU）。 调试方法包括从芯片组的系统管理中断引脚向中央处理单元发送系统管理中断信号。 然后CPU进入系统管理模式，并弹出一个调试操作窗口，用于选择和执行每个调试项目。 每个调试项目的执行完成后，CPU将离开调试操作窗口，并在调试前返回到下一条指令。 在调试操作窗口中完成每个调试项目的执行后，CPU将返回到操作系统，并在调试之前继续执行下一条指令。 调试的执行不会影响操作系统的状态和程序的执行。 所公开的调试方法可以随时执行每个调试项目。

公开(公告)号：US07293167B2

公开(公告)日：2007-11-06

申请号：US10965405

申请日：2004-10-14

Applicant: Yeh Cho ,  Chung-Ching Huang

Inventor： Yeh Cho ,  Chung-Ching Huang

IPC: G06F9/00 ,  G06F15/177 ,  G06F1/24

CPC classification number: G06F3/0632 ,  G06F3/0607 ,  G06F3/0676 ,  G06F9/4411

Abstract: A method and apparatus for driving a non-native SATA hard disk applied in a computer is provided. The computer includes a basic input/output system (BIOS) and an operating system (OS), both of which support an advanced configuration and power interface (ACPI). The non-native SATA hard disk includes a conversion interface and a parallel ATA (PATA) internal disk. First, issue an interrupt. Then, process an interrupt handle routine for detecting and saving the timing mode of the PATA internal disk. Next, load a default IDE driver. Then, report the saved timing mode. Finally, set the SATA hard disk according to the timing mode.

Abstract translation: 提供了一种用于驱动应用在计算机中的非本机SATA硬盘的方法和装置。 该计算机包括基本的输入/输出系统（BIOS）和操作系统（OS），两者都支持高级配置和电源接口（ACPI）。 非本机SATA硬盘包括转换接口和并行ATA（PATA）内部磁盘。 首先发出中断。 然后处理一个中断处理程序，用于检测和保存PATA内部磁盘的定时模式。 接下来，加载默认的IDE驱动程序。 然后，报告保存的定时模式。 最后，根据定时模式设置SATA硬盘。

公开(公告)号：US20050289369A1

公开(公告)日：2005-12-29

申请号：US10939573

申请日：2004-09-13

Applicant: Chien-Ping Chung ,  Chung-Ching Huang ,  Jing-Rung Wang

Inventor： Chien-Ping Chung ,  Chung-Ching Huang ,  Jing-Rung Wang

IPC: G06F1/26 ,  G06F1/32

CPC classification number: G06F1/3203 ,  G06F1/324 ,  G06F1/3287 ,  G06F1/3296 ,  Y02D10/126 ,  Y02D10/171 ,  Y02D10/172

Abstract: A system and method of real-time power management for use in computer systems. The system utilization is assessed by a North bridge, and a result is transferred to a South bridge. Thereafter, through transmitting sideband signals to a voltage controller and a frequency controller by sideband pins, the North Bridge provides faster and more efficient power management performance than the system management bus (SMBUS).

Abstract translation: 一种用于计算机系统的实时电源管理系统和方法。 系统利用率由北桥评估，结果转移到南桥。 此后，通过边带引脚将边带信号发送到电压控制器和频率控制器，北桥提供比系统管理总线（SMBUS）更快更有效的电源管理性能。