公开(公告)号：US11638378B2

公开(公告)日：2023-04-25

申请号：US17317872

申请日：2021-05-11

Applicant: Winbond Electronics Corp.

Inventor： Che-Fu Chuang ,  Hsiu-Han Liao

IPC: H10B41/40 ,  H10B41/49 ,  H01L21/311 ,  H01L21/3213

Abstract: A method for fabricating a semiconductor device includes: forming a first gate dielectric layer in a first and a second regions of a peripheral region of a substrate; forming a first conductive layer and a first hard mask layer over the substrate; forming a first mask layer on the first hard mask layer in the first region; removing the first hard mask layer outside the first region; removing the first hard mask layer; performing a wet etch process by taking the first hard mask layer as a mask, and removing the first conductive layer and the first gate dielectric layer outside the first region; removing the first hard mask layer and the first conductive layer; forming a second gate dielectric layer in the second region; and forming a first and a second gate conductive layers in the first and the second regions respectively.

公开(公告)号：US11380582B2

公开(公告)日：2022-07-05

申请号：US17061185

申请日：2020-10-01

Applicant: Winbond Electronics Corp.

Inventor： Che-Fu Chuang

IPC: H01L21/768 ,  H01L27/11521 ,  H01L29/66 ,  H01L21/28 ,  H01L21/8234

Abstract: A method for manufacturing a semiconductor device is provided. The method includes the following steps: forming a lining layer on a substrate and a plurality of gate structures; forming a first spacer layer on the lining layer; forming a stop layer on the first spacer layer; forming a first sacrificial layer on the stop layer and between the gate structures; removing a portion of the first sacrificial layer so that the top surface of the first sacrificial layer is located between the upper portions of the gate structures; forming a second spacer layer on the first sacrificial layer and the gate structures; and removing a portion of the second spacer layer so that the remaining second spacer layer is located between the upper portions of the gate structures.

公开(公告)号：US11004805B2

公开(公告)日：2021-05-11

申请号：US16542305

申请日：2019-08-16

Applicant: Winbond Electronics Corp.

Inventor： Yao-Ting Tsai ,  Chiang-Hung Chen ,  Che-Fu Chuang ,  Wen Hung

IPC: H01L23/00 ,  H01L21/74

Abstract: Provided is a method of fabricating a semiconductor device, including the following steps. A first seal ring and a second seal ring that are separated from each other are formed on a substrate. A protective layer covering the first seal ring and the second seal ring is formed on the substrate. The protective layer between the first seal ring and the second seal ring includes a concave surface. The protective layer at the concave surface and a portion of the protective layer on the first seal ring are removed to form a spacer on a sidewall of the first seal ring, and form an opening in the protective layer. The width of the opening is greater than the width of the first seal ring, and the opening exposes a top surface of the first seal ring and the spacer.

公开(公告)号：US20210050307A1

公开(公告)日：2021-02-18

申请号：US16542305

申请日：2019-08-16

Applicant: Winbond Electronics Corp.

Inventor： Yao-Ting Tsai ,  Chiang-Hung Chen ,  Che-Fu Chuang ,  Wen Hung

IPC: H01L23/00 ,  H01L21/74

Abstract: Provided is a method of fabricating a semiconductor device, including the following steps. A first seal ring and a second seal ring that are separated from each other are formed on a substrate. A protective layer covering the first seal ring and the second seal ring is formed on the substrate. The protective layer between the first seal ring and the second seal ring includes a concave surface. The protective layer at the concave surface and a portion of the protective layer on the first seal ring are removed to form a spacer on a sidewall of the first seal ring, and form an opening in the protective layer. The width of the opening is greater than the width of the first seal ring, and the opening exposes a top surface of the first seal ring and the spacer.

公开(公告)号：US12190981B2

公开(公告)日：2025-01-07

申请号：US17866558

申请日：2022-07-18

Applicant: Winbond Electronics Corp.

Inventor： Yao-Ting Tsai ,  Che-Fu Chuang

IPC: G11C8/12 ,  G11C5/06 ,  G11C29/00 ,  G11C29/24 ,  G11C29/52 ,  H10B41/10 ,  H10B41/42 ,  G11C8/14

Abstract: A memory array is provided. The memory array includes multiple memory blocks, each including multiple data storage regions and multiple groups of word lines. Each group of word lines extend across one of the memory blocks. The groups of word lines are connected to multiple overlying signal lines through multiple groups of first word line contact regions in the memory blocks and multiple second word line contact regions between the memory blocks.

公开(公告)号：US11877447B2

公开(公告)日：2024-01-16

申请号：US18297659

申请日：2023-04-10

Applicant: Winbond Electronics Corp.

Inventor： Yao-Ting Tsai ,  Hsiu-Han Liao ,  Che-Fu Chuang

IPC: H01L21/00 ,  H10B41/42 ,  H01L29/66 ,  H01L29/788 ,  H10B41/30

CPC classification number: H10B41/42 ,  H01L29/66825 ,  H01L29/7883 ,  H10B41/30

Abstract: Disposed are a semiconductor structure, a manufacturing method thereof and a flash memory. The semiconductor structure includes a substrate, first isolation structures, a gate structure and an oxide layer. The first isolation structures define a first active area in a peripheral region of the substrate. The oxide layer is disposed on the substrate in the first active area and covered by the first isolation structures. The oxide layer and the first isolation structures define an opening exposing the substrate. The gate structure is disposed on the substrate in the first active area and includes a gate dielectric layer disposed in the opening and a gate disposed on the gate dielectric layer. The oxide layer is located around the gate dielectric layer. The width of the bottom surface of the gate is less than that of the top surface of the first active area.

公开(公告)号：US20230255026A1

公开(公告)日：2023-08-10

申请号：US18297659

申请日：2023-04-10

Applicant: Winbond Electronics Corp.

Inventor： Yao-Ting Tsai ,  Hsiu-Han Liao ,  Che-Fu Chuang

IPC: H10B41/42 ,  H01L29/66 ,  H01L29/788 ,  H10B41/30

CPC classification number: H10B41/42 ,  H01L29/66825 ,  H01L29/7883 ,  H10B41/30

Abstract: Disposed are a semiconductor structure, a manufacturing method thereof and a flash memory. The semiconductor structure includes a substrate, first isolation structures, a gate structure and an oxide layer. The first isolation structures define a first active area in a peripheral region of the substrate. The oxide layer is disposed on the substrate in the first active area and covered by the first isolation structures. The oxide layer and the first isolation structures define an opening exposing the substrate. The gate structure is disposed on the substrate in the first active area and includes a gate dielectric layer disposed in the opening and a gate disposed on the gate dielectric layer. The oxide layer is located around the gate dielectric layer. The width of the bottom surface of the gate is less than that of the top surface of the first active area.

公开(公告)号：US20230209820A1

公开(公告)日：2023-06-29

申请号：US17564259

申请日：2021-12-29

Applicant: Winbond Electronics Corp.

Inventor： Che-Fu Chuang ,  Yao-Ting Tsai ,  Hsiu-Han Liao

IPC: H01L27/11521 ,  H01L29/417 ,  H01L29/788 ,  H01L29/40 ,  H01L29/66

CPC classification number: H01L27/11521 ,  H01L29/41725 ,  H01L29/7883 ,  H01L29/401 ,  H01L29/66825

Abstract: Provided are a memory device and a method of manufacturing the same. The memory device includes: a stack structure; a first source/drain region and a second source/drain region located in a substrate beside the stack structure; a first self-aligned contact connected to the first source/drain region; a second self-aligned contact connected to the second source/drain region; a first liner structure located between the first self-aligned contact and a first sidewall of the stack structure; and a second liner structure located between the second self-aligned contact and a second sidewall of the stack structure. The first liner structure and the second liner structure are not connected and do not cover the stack structure.

公开(公告)号：US11678484B2

公开(公告)日：2023-06-13

申请号：US17376079

申请日：2021-07-14

Applicant: Winbond Electronics Corp.

Inventor： Yao-Ting Tsai ,  Hsiu-Han Liao ,  Che-Fu Chuang

IPC: H01L21/00 ,  H10B41/42 ,  H01L29/66 ,  H01L29/788 ,  H10B41/30

CPC classification number: H10B41/42 ,  H01L29/66825 ,  H01L29/7883 ,  H10B41/30

Abstract: Disposed are a semiconductor structure, a manufacturing method thereof and a flash memory. The semiconductor structure includes a substrate, first isolation structures, a gate structure and an oxide layer. The first isolation structures define a first active area in a peripheral region of the substrate. The oxide layer is disposed on the substrate in the first active area and covered by the first isolation structures. The oxide layer and the first isolation structures define an opening exposing the substrate. The gate structure is disposed on the substrate in the first active area and includes a gate dielectric layer disposed in the opening and a gate disposed on the gate dielectric layer. The oxide layer is located around the gate dielectric layer. The width of the bottom surface of the gate is less than that of the top surface of the first active area.

公开(公告)号：US11362098B2

公开(公告)日：2022-06-14

申请号：US17061442

申请日：2020-10-01

Applicant: Winbond Electronics Corp.

Inventor： Che-Fu Chuang ,  Jian-Ting Chen ,  Yu-Kai Liao ,  Hsiu-Han Liao

IPC: H01L27/11517 ,  H01L29/66

Abstract: A method for manufacturing a memory device is provided. The method includes the following steps: providing a substrate; forming a plurality of first gate structures; forming a lining layer on the substrate; forming a spacer layer on the lining layer; forming a stop layer on the spacer layer; forming a first sacrificial layer on the stop layer; removing a portion of the first sacrificial layer to expose the stop layer on the first gate structures, and to expose the stop layer at the bottoms of the trenches; removing the stop layer at the bottoms of the trenches to expose the spacer layer; removing the remaining first sacrificial layer; forming a second sacrificial layer on the substrate; and removing the second sacrificial layer, and removing the spacer layer and the lining layer at the bottoms of the plurality of trenches to expose the substrate.