公开(公告)号：US10854624B2

公开(公告)日：2020-12-01

申请号：US16358708

申请日：2019-03-20

Applicant: Winbond Electronics Corp.

Inventor： Wen Hung ,  Yu-Kai Liao ,  Chiang-Hung Chen

IPC: H01L27/11548 ,  H01L27/11573 ,  H01L27/11526 ,  H01L21/033 ,  H01L21/311 ,  H01L21/28

Abstract: Provided is a semiconductor memory device including a substrate, an isolation structure, a first gate dielectric layer, a first conductive layer, a second gate dielectric layer, a second conductive layer, and a protective layer. The substrate has an array region and a periphery region. The isolation structure is disposed in the substrate between the array and periphery regions. The first gate dielectric layer is disposed on the substrate in the array region. The first conductive layer is disposed on the first gate dielectric layer. The second gate dielectric layer is disposed on the substrate in the periphery region. The second conductive layer is disposed on the second dielectric layer. The second conductive layer extends to cover a portion of a top surface of the isolation structure. The protective layer is disposed between the second conductive layer and the isolation structure.

公开(公告)号：US11417678B2

公开(公告)日：2022-08-16

申请号：US17080831

申请日：2020-10-26

Applicant: Winbond Electronics Corp.

Inventor： Wen Hung ,  Yu-Kai Liao ,  Chiang-Hung Chen

IPC: H01L21/762 ,  H01L27/11573 ,  H01L27/11526 ,  H01L21/033 ,  H01L21/311 ,  H01L21/28

Abstract: Provided is a semiconductor memory device including a substrate, an isolation structure, a first gate dielectric layer, a first conductive layer, a second gate dielectric layer, a second conductive layer, and a protective layer. The substrate has an array region and a periphery region. The isolation structure is disposed in the substrate between the array and periphery regions. The first gate dielectric layer is disposed on the substrate in the array region. The first conductive layer is disposed on the first gate dielectric layer. The second gate dielectric layer is disposed on the substrate in the periphery region. The second conductive layer is disposed on the second dielectric layer. The second conductive layer extends to cover a portion of a top surface of the isolation structure. The protective layer is disposed between the second conductive layer and the isolation structure.

公开(公告)号：US20190043569A1

公开(公告)日：2019-02-07

申请号：US16048364

申请日：2018-07-30

Applicant: Winbond Electronics Corp.

Inventor： Chiang-Hung Chen ,  Yao-Ting Tsai ,  Wen Hung ,  Yu-Kai Liao

IPC: G11C11/56 ,  H01L23/528 ,  H01L23/532 ,  H01L29/51 ,  G11C16/10 ,  G11C16/14 ,  G11C16/26 ,  H01L27/11582 ,  G11C16/04 ,  H01L21/762 ,  H01L21/3105 ,  H01L21/768 ,  H01L21/02 ,  H01L21/311 ,  H01L21/28 ,  H01L21/3213 ,  H01L21/3215

Abstract: Provided is a three dimensional memory including a substrate, a plurality of source lines, a plurality of isolation structures, a plurality of drain lines, a plurality of bit lines, a plurality of charge storage structures, and a plurality of conductive layers. The source lines are located on the substrate. The isolation structures are respectively located between the source lines, so as to electrically isolate the source lines from each other. The drain lines are located on the source lines. Extending directions of the source lines and the drain lines are different. The bit lines extend from the source lines to the drain lines. The charge storage structures respectively surround the bit lines. The conductive layer respectively cover surfaces of the charge storage structures arranged along each of the source lines.

公开(公告)号：US20210043642A1

公开(公告)日：2021-02-11

申请号：US17080831

申请日：2020-10-26

Applicant: Winbond Electronics Corp.

Inventor： Wen Hung ,  Yu-Kai Liao ,  Chiang-Hung Chen

IPC: H01L27/11573 ,  H01L21/28 ,  H01L27/11526 ,  H01L21/033 ,  H01L21/311

Abstract: Provided is a semiconductor memory device including a substrate, an isolation structure, a first gate dielectric layer, a first conductive layer, a second gate dielectric layer, a second conductive layer, and a protective layer. The substrate has an array region and a periphery region. The isolation structure is disposed in the substrate between the array and periphery regions. The first gate dielectric layer is disposed on the substrate in the array region. The first conductive layer is disposed on the first gate dielectric layer. The second gate dielectric layer is disposed on the substrate in the periphery region. The second conductive layer is disposed on the second dielectric layer. The second conductive layer extends to cover a portion of a top surface of the isolation structure. The protective layer is disposed between the second conductive layer and the isolation structure.

公开(公告)号：US10580487B2

公开(公告)日：2020-03-03

申请号：US16048364

申请日：2018-07-30

Applicant: Winbond Electronics Corp.

Inventor： Chiang-Hung Chen ,  Yao-Ting Tsai ,  Wen Hung ,  Yu-Kai Liao

IPC: G11C11/56 ,  H01L21/3215 ,  H01L23/532 ,  H01L29/51 ,  G11C16/10 ,  G11C16/14 ,  G11C16/26 ,  H01L27/11582 ,  G11C16/04 ,  H01L21/762 ,  H01L21/3105 ,  H01L21/768 ,  H01L21/02 ,  H01L21/311 ,  H01L21/3213 ,  H01L23/528 ,  H01L21/28 ,  H01L29/423 ,  H01L27/11521 ,  H01L29/66 ,  H01L29/788

Abstract: A three dimensional memory includes a substrate, a plurality of source lines, a plurality of isolation structures, a plurality of drain lines, a plurality of bit lines, a plurality of charge storage structures, and a plurality of conductive layers. The source lines are located on the substrate. The isolation structures are respectively located between the source lines, so as to electrically isolate the source lines from each other. The drain lines are located on the source lines. Extending directions of the source lines and the drain lines are different. The bit lines extend from the source lines to the drain lines. The charge storage structures respectively surround the bit lines. The conductive layers respectively cover surfaces of the charge storage structures arranged along each of the source lines.

公开(公告)号：US11362098B2

公开(公告)日：2022-06-14

申请号：US17061442

申请日：2020-10-01

Applicant: Winbond Electronics Corp.

Inventor： Che-Fu Chuang ,  Jian-Ting Chen ,  Yu-Kai Liao ,  Hsiu-Han Liao

IPC: H01L27/11517 ,  H01L29/66

Abstract: A method for manufacturing a memory device is provided. The method includes the following steps: providing a substrate; forming a plurality of first gate structures; forming a lining layer on the substrate; forming a spacer layer on the lining layer; forming a stop layer on the spacer layer; forming a first sacrificial layer on the stop layer; removing a portion of the first sacrificial layer to expose the stop layer on the first gate structures, and to expose the stop layer at the bottoms of the trenches; removing the stop layer at the bottoms of the trenches to expose the spacer layer; removing the remaining first sacrificial layer; forming a second sacrificial layer on the substrate; and removing the second sacrificial layer, and removing the spacer layer and the lining layer at the bottoms of the plurality of trenches to expose the substrate.

公开(公告)号：US20200303394A1

公开(公告)日：2020-09-24

申请号：US16358708

申请日：2019-03-20

Applicant: Winbond Electronics Corp.

Inventor： Wen Hung ,  Yu-Kai Liao ,  Chiang-Hung Chen

IPC: H01L27/11573 ,  H01L27/11526 ,  H01L21/311 ,  H01L21/28 ,  H01L21/033

Abstract: Provided is a semiconductor memory device including a substrate, an isolation structure, a first gate dielectric layer, a first conductive layer, a second gate dielectric layer, a second conductive layer, and a protective layer. The substrate has an array region and a periphery region. The isolation structure is disposed in the substrate between the array and periphery regions. The first gate dielectric layer is disposed on the substrate in the array region. The first conductive layer is disposed on the first gate dielectric layer. The second gate dielectric layer is disposed on the substrate in the periphery region. The second conductive layer is disposed on the second dielectric layer. The second conductive layer extends to cover a portion of a top surface of the isolation structure. The protective layer is disposed between the second conductive layer and the isolation structure.

公开(公告)号：US20200243143A1

公开(公告)日：2020-07-30

申请号：US16684591

申请日：2019-11-15

Applicant: Winbond Electronics Corp.

Inventor： Yu-Kai Liao ,  Chiang-Hung Chen ,  Wen Hung

IPC: G11C16/14 ,  G11C16/34 ,  G11C16/04

Abstract: An erasing method adapted for a semiconductor memory device is provided. The erasing method includes executing a pre-program process on the semiconductor memory device, executing an erase process on the semiconductor memory device, executing an over-erase verification process on a plurality of memory cells of the semiconductor memory device, detecting a total current consumption of the plurality of memory cells, determining the number of the memory cells to be executed with a soft program process according to the total current consumption, and executing the soft program process on the memory cells based on the number of the memory cells.